49 lines
1.7 KiB
Diff
49 lines
1.7 KiB
Diff
From 3cdf8aa3ff45e35a237285c107785bc3d2c6976a Mon Sep 17 00:00:00 2001
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From: Ludwig Kormann <ludwig.kormann@ict42.de>
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Date: Wed, 31 Jan 2024 11:28:19 +0100
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Subject: [PATCH] sunxi: sun4i: Reduce cpu clock at SPL initialization to 144
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MHz
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Up until now cpu clock gets initialized at 384 MHz, which is
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the highest supported cpu clock.
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Recent A20 batches show an increased percentage of modules
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reacting very sensitive to operating conditions outside the
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specifications.
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The cpu dies very shortly after PLLs, core frequency or cpu
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voltage are missconfigured. E.g.:
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- uboot SPL selects 384 MHz as cpu clock which requires a cpu
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voltage of at least 1.1 V.
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- Linux CPU Frequency scaling with most sun7i dts will reduce
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cpu voltage down to 1.0 V.
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- When intiating a reboot or reset from linux the cpu voltage
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may keep the 1.0 V configuration and the cpu dies during SPL
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initialization.
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Therefore reduce cpu clock at uboot SPL initialization down
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to 144 MHz from 384 MHz.
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Signed-off-by: Ludwig Kormann <ludwig.kormann@ict42.de>
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Upstream: Not Applicable
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---
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arch/arm/include/asm/arch-sunxi/clock_sun4i.h | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
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index 2cec91cb20..252c4c693e 100644
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--- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
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+++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
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@@ -141,7 +141,7 @@ struct sunxi_ccm_reg {
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#define CCM_PLL1_CFG_SIG_DELT_PAT_EN_SHIFT 2
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#define CCM_PLL1_CFG_FACTOR_M_SHIFT 0
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-#define PLL1_CFG_DEFAULT 0xa1005000
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+#define PLL1_CFG_DEFAULT 0xa1004c01
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#if defined CONFIG_OLD_SUNXI_KERNEL_COMPAT && defined CONFIG_MACH_SUN5I
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/*
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--
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2.39.2
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