from z80shortcuts import *

instructions = [None] * 256

y = 0
z = 0
instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
    "name": "NOP",
    "subins": [
        c_qw["reset_m_state"] | c_qw["reset_context"]
    ]
}

y = 1
z = 0
instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
    "name": "EX AF, AF'",
    "subins": [
        c_qw["AF_toggle"] | c_qw["reset_m_state"] | c_qw["reset_context"]
    ]
}

y = 2
z = 0
instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
    "name": "DJNZ d",
    "subins": [
        sr_read(sr.index("PC")) | mem_read | c_qw["ACU_write_en"] | c_qw["TMP_write_en"] | sr_write(sr.index("Z")),
        sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),

        #sign extend
        alu_op(alu.index("ADD")),
        alu_op(alu.index("SBC")) | sr_write(sr.index("W")),

        sr_read(sr.index("PCL")) | c_qw["ACU_write_en"],
        sr_read(sr.index("Z")) | c_qw["TMP_write_en"],
        alu_op(alu.index("ADD")) | sr_write(sr.index("Z")),
        sr_read(sr.index("PCH")) | c_qw["ACU_write_en"],
        sr_read(sr.index("W")) | c_qw["TMP_write_en"],
        alu_op(alu.index("ADC")) | sr_write(sr.index("W")),
        clear_acu,
        mr_read(r.index("B")) | c_qw["TMP_write_en"],
        alu_op(inc.index("DEC"),alu_dev.index("INC")) | mr_write(r.index("B")),
        exec_if_cond(cc_i["NZ"]) | c_qw["reset_m_state"] | c_qw["reset_context"],
        sr_read(sr.index("WZ")) | sr_write(sr.index("PC")) | c_qw["reset_m_state"] | c_qw["reset_context"]
    ]
}

y = 3
z = 0
instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
    "name": "JR d",
            "subins": [
                sr_read(sr.index("PC")) | mem_read | c_qw["ACU_write_en"] | c_qw["TMP_write_en"] | sr_write(sr.index("Z")),
                sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),

                #sign extend
                alu_op(alu.index("ADD")),
                alu_op(alu.index("SBC")) | sr_write(sr.index("W")),

                sr_read(sr.index("PCL")) | c_qw["ACU_write_en"],
                sr_read(sr.index("Z")) | c_qw["TMP_write_en"],
                alu_op(alu.index("ADD")) | sr_write(sr.index("Z")),
                sr_read(sr.index("PCH")) | c_qw["ACU_write_en"],
                sr_read(sr.index("W")) | c_qw["TMP_write_en"],
                alu_op(alu.index("ADC")) | sr_write(sr.index("W")),

                sr_read(sr.index("WZ")) | sr_write(sr.index("PC")) | c_qw["reset_m_state"] | c_qw["reset_context"]
            ]
}



z = 0
for y in [4, 5, 6, 7]:
    instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
        "name": f"JR {cc[y-4]}, d",
        "subins": [
            sr_read(sr.index("PC")) | mem_read | c_qw["ACU_write_en"] | c_qw["TMP_write_en"] | sr_write(sr.index("Z")),
            sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),

            #early return
            f_to_flatch,
            exec_if_cond(cc_i[cc[(y-4)]]) | c_qw["reset_m_state"] | c_qw["reset_context"],

            #sign extend
            alu_op(alu.index("ADD")),
            alu_op(alu.index("SBC")) | sr_write(sr.index("W")),

            sr_read(sr.index("PCL")) | c_qw["ACU_write_en"],
            sr_read(sr.index("Z")) | c_qw["TMP_write_en"], # unneeded
            alu_op(alu.index("ADD")) | sr_write(sr.index("Z")),
            sr_read(sr.index("PCH")) | c_qw["ACU_write_en"],
            sr_read(sr.index("W")) | c_qw["TMP_write_en"],
            alu_op(alu.index("ADC")) | sr_write(sr.index("W")),

            sr_read(sr.index("WZ")) | sr_write(sr.index("PC")) | c_qw["reset_m_state"] | c_qw["reset_context"]
        ]
    }
    

z = 1
for y in range(8):
    p = y >> 1
    q = y & 1
    if q != 0: continue
    if p == 3: continue
    instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
        "name": f"LD {rp[p]}, nn",
        "subins": [
            sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")) | mem_read | mr_write((p<<1)+1),
            sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")) | mem_read | mr_write((p<<1)) | c_qw["reset_m_state"] | c_qw["reset_context"]
        ]
    }

z = 1
y = 6
instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
    "name": f"LD SP, nn",
    "subins": [
        sr_read(sr.index("PC")) | mem_read | sr_write(sr.index("SPL")),
        sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
        sr_read(sr.index("PC")) | mem_read | sr_write(sr.index("SPH")),
        sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")) | c_qw["reset_m_state"] | c_qw["reset_context"]
    ]
}

z = 1
for y in range(8):
    p = y >> 1
    q = y & 1
    if q == 0: continue
    if p == 3: continue
    instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
        "name": f"ADD HL, {rp[p]}",
        "subins": [
            mr_read(r.index("L")) | c_qw["ACU_write_en"],
            mr_read((p<<1)+1) | c_qw["TMP_write_en"],
            alu_op(alu.index("ADD")) | mr_write(r.index("L")),
            mr_read(r.index("H")) | c_qw["ACU_write_en"],
            mr_read((p<<1)) | c_qw["TMP_write_en"],
            alu_op(alu.index("ADC")) | mr_write(r.index("H")),
            flatch_to_f | c_qw["reset_m_state"] | c_qw["reset_context"]
        ]
    }

z = 1
p = rp.index("SP")
q = 1
instructions[int(f"0b00{((p<<1)+q):03b}{z:03b}", 2)] = {
    "name": f"ADD HL, SP",
    "subins": [
        mr_read(r.index("L")) | c_qw["ACU_write_en"],
        sr_read(sr.index("SPL")) | c_qw["TMP_write_en"],
        alu_op(alu.index("ADD")) | mr_write(r.index("L")),
        mr_read(r.index("H")) | c_qw["ACU_write_en"],
        sr_read(sr.index("SPH")) | c_qw["TMP_write_en"],
        alu_op(alu.index("ADC")) | mr_write(r.index("H")),
        flatch_to_f | c_qw["reset_m_state"] | c_qw["reset_context"]
    ]
}

z = 2
q = 0
p = 0
instructions[int(f"0b00{((p<<1)+q):03b}{z:03b}", 2)] = {
    "name": f"LD (BC), A",
    "subins": [
        mr_read(r.index("B")) | sr_write(sr.index("W")),
        mr_read(r.index("C")) | sr_write(sr.index("Z")),
        sr_read(sr.index("WZ")) | mr_read(r.index("A")) | mem_write | c_qw["reset_m_state"] | c_qw["reset_context"]
    ]
}

z = 2
q = 0
p = 1
instructions[int(f"0b00{((p<<1)+q):03b}{z:03b}", 2)] = {
    "name": f"LD (DE), A",
    "subins": [
        mr_read(r.index("D")) | sr_write(sr.index("W")),
        mr_read(r.index("E")) | sr_write(sr.index("Z")),
        sr_read(sr.index("WZ")) | mr_read(r.index("A")) | mem_write | c_qw["reset_m_state"] | c_qw["reset_context"]
    ]
}

z = 2
q = 0
p = 2
instructions[int(f"0b00{((p<<1)+q):03b}{z:03b}", 2)] = {
    "name": f"LD (nn), HL",
    "subins": [
        sr_read(sr.index("PC")) | mem_read | sr_write(sr.index("Z")),
        sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
        sr_read(sr.index("PC")) | mem_read | sr_write(sr.index("W")),
        sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
        sr_read(sr.index("WZ")) | mr_read(r.index("L")) | mem_write | c_qw["addr_inc_en"] | sr_write(sr.index("WZ")),
        sr_read(sr.index("WZ")) | mr_read(r.index("H")) | mem_write | c_qw["reset_m_state"] | c_qw["reset_context"]
    ]
}

z = 2
q = 0
p = 3
instructions[int(f"0b00{((p<<1)+q):03b}{z:03b}", 2)] = {
    "name": f"LD (nn), A",
    "subins": [
        sr_read(sr.index("PC")) | mem_read | sr_write(sr.index("Z")),
        sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
        sr_read(sr.index("PC")) | mem_read | sr_write(sr.index("W")),
        sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
        sr_read(sr.index("WZ")) | mr_read(r.index("A")) | mem_write | c_qw["reset_m_state"] | c_qw["reset_context"]
    ]
}

z = 2
q = 1
p = 0
instructions[int(f"0b00{((p<<1)+q):03b}{z:03b}", 2)] = {
    "name": f"LD A, (BC)",
    "subins": [
        mr_read(r.index("B")) | sr_write(sr.index("W")),
        mr_read(r.index("C")) | sr_write(sr.index("Z")),
        sr_read(sr.index("WZ")) | mem_read | mr_write(r.index("A")) | c_qw["reset_m_state"] | c_qw["reset_context"]
    ]
}
z = 2
q = 1
p = 1
instructions[int(f"0b00{((p<<1)+q):03b}{z:03b}", 2)] = {
    "name": f"LD A, (DE)",
    "subins": [
        mr_read(r.index("D")) | sr_write(sr.index("W")),
        mr_read(r.index("E")) | sr_write(sr.index("Z")),
        sr_read(sr.index("WZ")) | mem_read | mr_write(r.index("A")) | c_qw["reset_m_state"] | c_qw["reset_context"]
    ]
}
z = 2
q = 1
p = 2
instructions[int(f"0b00{((p<<1)+q):03b}{z:03b}", 2)] = {
    "name": f"LD HL, (nn)",
    "subins": [
        sr_read(sr.index("PC")) | mem_read |sr_write(sr.index("Z")),
        sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
        sr_read(sr.index("PC")) | mem_read | sr_write(sr.index("W")),
        sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
        sr_read(sr.index("WZ")) | mem_read | mr_write(r.index("L")),
        sr_read(sr.index("WZ")) | c_qw["addr_inc_en"] | sr_write(sr.index("WZ")),
        sr_read(sr.index("WZ")) | mem_read | mr_write(r.index("H")) | c_qw["reset_m_state"] | c_qw["reset_context"]
    ]
}
z = 2
q = 1
p = 3
instructions[int(f"0b00{((p<<1)+q):03b}{z:03b}", 2)] = {
    "name": f"LD A, (nn)",
    "subins": [
        sr_read(sr.index("PC")) | mem_read | sr_write(sr.index("Z")),
        sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
        sr_read(sr.index("PC")) | mem_read | sr_write(sr.index("W")),
        sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
        sr_read(sr.index("WZ")) | mem_read | mr_write(r.index("A")) | c_qw["reset_m_state"] | c_qw["reset_context"]
    ]
}

z = 3
q = 0
for p in range(3):
    instructions[int(f"0b00{((p<<1)+q):03b}{z:03b}", 2)] = {
        "name": f"INC {rp[p]}",
        "subins": [
            clear_acu,
            mr_read((p<<1)+1) | c_qw["TMP_write_en"],
            alu_op(inc.index("INC"),alu_dev.index("INC")) | mr_write((p<<1)+1),
            mr_read((p<<1)) | c_qw["TMP_write_en"],
            alu_op(alu.index("ADC")) | mr_write((p<<1)) | c_qw["reset_m_state"] | c_qw["reset_context"]
        ]
    }

z = 3
q = 0
p = rp.index("SP")
instructions[int(f"0b00{((p<<1)+q):03b}{z:03b}", 2)] = {
    "name": f"INC SP",
    "subins": [
        clear_acu,
        sr_read(sr.index("SPL")) | c_qw["TMP_write_en"],
        alu_op(inc.index("INC"),alu_dev.index("INC")) | sr_write(sr.index("SPL")),
        sr_read(sr.index("SPH")) | c_qw["TMP_write_en"],
        alu_op(alu.index("ADC")) | sr_write(sr.index("SPH")) | c_qw["reset_m_state"] | c_qw["reset_context"]
    ]
}

z = 3
q = 1
for p in range(2):
    instructions[int(f"0b00{((p<<1)+q):03b}{z:03b}", 2)] = {
        "name": f"DEC {rp[p]}",
        "subins": [
            clear_acu,
            mr_read((p<<1)+1) | c_qw["TMP_write_en"],
            alu_op(inc.index("DEC"),alu_dev.index("INC")) | mr_write((p<<1)+1),
            clear_tmp,
            mr_read((p<<1)) | c_qw["ACU_write_en"],
            alu_op(alu.index("SBC")) | mr_write((p<<1)) | c_qw["reset_m_state"] | c_qw["reset_context"]
        ]
    }

z = 3
q = 1
p = rp.index("SP")
instructions[int(f"0b00{((p<<1)+q):03b}{z:03b}", 2)] = {
    "name": f"DEC SP",
    "subins": [
        clear_acu,
        sr_read(sr.index("SPL")) | c_qw["TMP_write_en"],
        alu_op(inc.index("DEC"),alu_dev.index("INC")) | sr_write(sr.index("SPL")),
        clear_tmp,
        sr_read(sr.index("SPH")) | c_qw["ACU_write_en"],
        alu_op(alu.index("SBC")) | sr_write(sr.index("SPH")) | c_qw["reset_m_state"] | c_qw["reset_context"]
    ]
}


z = 4
for y in range(8):
    if y == r.index("(HL)"): continue
    instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
        "name": f"INC {r[y]}",
        "subins": [
            clear_acu,
            mr_read(y) | c_qw["TMP_write_en"],
            alu_op(inc.index("INC"),alu_dev.index("INC")) | mr_write(y),
            flatch_to_f | c_qw["reset_m_state"] | c_qw["reset_context"]
        ]
    }

z = 4
y = r.index("(HL)")
instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
   "name": f"INC (HL)",
   "subins": [
        exec_if_context | sr_read(sr.index("PC")) | mem_read | c_qw["ACU_write_en"] | c_qw["TMP_write_en"] | sr_write(sr.index("Z")),
        exec_if_context | sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),

        #sign extend
        exec_if_context | alu_op(alu.index("ADD")),
        exec_if_context | alu_op(alu.index("SBC")) | sr_write(sr.index("W")),

        exec_if_context | mr_read(r.index("L")) | c_qw["ACU_write_en"],
        exec_if_context | sr_read(sr.index("Z")) | c_qw["TMP_write_en"],
        exec_if_context | alu_op(alu.index("ADD")) | sr_write(sr.index("Z")),
        exec_if_context | mr_read(r.index("H")) | c_qw["ACU_write_en"],
        exec_if_context | sr_read(sr.index("W")) | c_qw["TMP_write_en"],
        exec_if_context | alu_op(alu.index("ADC")) | sr_write(sr.index("W")),

        clear_acu,
        mr_read(r.index("(HL)")) | mem_read | c_qw["TMP_write_en"],
        alu_op(inc.index("INC"),alu_dev.index("INC")) | mr_read(y) | mem_write,
        flatch_to_f | c_qw["reset_m_state"] | c_qw["reset_context"]
    ]
}

z = 5
for y in range(8):
    if y == r.index("(HL)"): continue
    instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
        "name": f"DEC {r[y]}",
        "subins": [
            clear_acu,
            mr_read(y) | c_qw["TMP_write_en"],
            alu_op(inc.index("DEC"),alu_dev.index("INC")) | mr_write(y),
            flatch_to_f | c_qw["reset_m_state"] | c_qw["reset_context"]
        ]
    }

z = 5
y = r.index("(HL)")
instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
   "name": f"DEC (HL)",
   "subins": [
        exec_if_context | sr_read(sr.index("PC")) | mem_read | c_qw["ACU_write_en"] | c_qw["TMP_write_en"] | sr_write(sr.index("Z")),
        exec_if_context | sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),

        #sign extend
        exec_if_context | alu_op(alu.index("ADD")),
        exec_if_context | alu_op(alu.index("SBC")) | sr_write(sr.index("W")),

        exec_if_context | mr_read(r.index("L")) | c_qw["ACU_write_en"],
        exec_if_context | sr_read(sr.index("Z")) | c_qw["TMP_write_en"],
        exec_if_context | alu_op(alu.index("ADD")) | sr_write(sr.index("Z")),
        exec_if_context | mr_read(r.index("H")) | c_qw["ACU_write_en"],
        exec_if_context | sr_read(sr.index("W")) | c_qw["TMP_write_en"],
        exec_if_context | alu_op(alu.index("ADC")) | sr_write(sr.index("W")),

        clear_acu,
        mr_read(r.index("(HL)")) | mem_read | c_qw["TMP_write_en"],
        alu_op(inc.index("DEC"),alu_dev.index("INC")) | mr_read(y) | mem_write,
        flatch_to_f | c_qw["reset_m_state"] | c_qw["reset_context"]
    ]
}

z = 6
for y in range(8):
    if y == r.index("(HL)"): continue
    instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
        "name": f"LD {r[y]}, n",
        "subins": [
            sr_read(sr.index("PC")) | mem_read | mr_write(y) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")) | c_qw["reset_m_state"] | c_qw["reset_context"]
        ]
    }

z = 6
y = r.index("(HL)")
instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
   "name": f"LD (HL), n",
   "subins": [
        exec_if_context | sr_read(sr.index("PC")) | mem_read | c_qw["ACU_write_en"] | c_qw["TMP_write_en"] | sr_write(sr.index("Z")),
        exec_if_context | sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),

        #sign extend
        exec_if_context | alu_op(alu.index("ADD")),
        exec_if_context | alu_op(alu.index("SBC")) | sr_write(sr.index("W")),

        exec_if_context | mr_read(r.index("L")) | c_qw["ACU_write_en"],
        exec_if_context | sr_read(sr.index("Z")) | c_qw["TMP_write_en"],
        exec_if_context | alu_op(alu.index("ADD")) | sr_write(sr.index("Z")),
        exec_if_context | mr_read(r.index("H")) | c_qw["ACU_write_en"],
        exec_if_context | sr_read(sr.index("W")) | c_qw["TMP_write_en"],
        exec_if_context | alu_op(alu.index("ADC")) | sr_write(sr.index("W")),

        sr_read(sr.index("PC")) | mem_read | c_qw["TMP_write_en"] | c_qw["addr_inc_en"] | sr_write(sr.index("PC")), # super hacky to preserve WZ for (IX+d)

        mr_read(r.index("(HL)")) | tmp_to_db | mem_write | c_qw["reset_m_state"] | c_qw["reset_context"] # passthru tmp => DB
    ]
}

z = 7
y = 0
instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
   "name": "RLCA",
   "subins": [
        f_to_flatch,
        mr_read(r.index("A")) | c_qw["TMP_write_en"],
        alu_op(rot.index("RLC"),alu_dev.index("SLU")) | mr_write(r.index("A")),

        c_qw["Flatch_read_en"] | c_qw["ACU_write_en"],
        clear_tmp,
        alu_op(flags.index("C") | bit["SET"],alu_dev.index("BMU")) | c_qw["TMP_write_en"],
        alu_op(alu.index("AND")) | sr_write(sr.index("Z")),

        internal_byte_to_db(internal_byte.index("FF")) | c_qw["TMP_write_en"],
        alu_op(flags.index("C") | bit["RESET"],alu_dev.index("BMU")) | c_qw["TMP_write_en"],
        alu_op(flags.index("H") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
        alu_op(flags.index("N") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"], #W = 0b11101100
        c_qw["F_read_en"] | c_qw["ACU_write_en"],
        alu_op(alu.index("AND")) | c_qw["ACU_write_en"],

        sr_write(sr.index("Z")) | c_qw["TMP_write_en"],
        alu_op(alu.index("OR")) | c_qw["F_write_en"]| c_qw["reset_m_state"] | c_qw["reset_context"]
    ]
}

z = 7
y = 1
instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
   "name": "RRCA",
   "subins": [
        f_to_flatch,
        mr_read(r.index("A")) | c_qw["TMP_write_en"],
        alu_op(rot.index("RRC"),alu_dev.index("SLU")) | mr_write(r.index("A")),

        c_qw["Flatch_read_en"] | c_qw["ACU_write_en"],
        clear_tmp,
        alu_op(flags.index("C") | bit["SET"],alu_dev.index("BMU")) | c_qw["TMP_write_en"],
        alu_op(alu.index("AND")) | sr_write(sr.index("Z")), # Z = 0b0000000C

        internal_byte_to_db(internal_byte.index("FF")) | c_qw["TMP_write_en"],
        alu_op(flags.index("C") | bit["RESET"],alu_dev.index("BMU")) | c_qw["TMP_write_en"],
        alu_op(flags.index("H") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
        alu_op(flags.index("N") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"], #W = 0b11101100
        c_qw["F_read_en"] | c_qw["ACU_write_en"],
        alu_op(alu.index("AND")) | c_qw["ACU_write_en"],

        sr_write(sr.index("Z")) | c_qw["TMP_write_en"],
        alu_op(alu.index("OR")) | c_qw["F_write_en"]| c_qw["reset_m_state"] | c_qw["reset_context"]
    ]
}

z = 7
y = 2
instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
   "name": "RLA",
   "subins": [
        mr_read(r.index("A")) | c_qw["TMP_write_en"],
        alu_op(rot.index("RL"),alu_dev.index("SLU"))| mr_write(r.index("A")),

        c_qw["Flatch_read_en"] | c_qw["ACU_write_en"],
        clear_tmp,
        alu_op(flags.index("C") | bit["SET"],alu_dev.index("BMU")) | c_qw["TMP_write_en"],
        alu_op(alu.index("AND")) | sr_write(sr.index("Z")), # Z = 0b0000000C

        internal_byte_to_db(internal_byte.index("FF")) | c_qw["TMP_write_en"],
        alu_op(flags.index("C") | bit["RESET"],alu_dev.index("BMU")) | c_qw["TMP_write_en"],
        alu_op(flags.index("H") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
        alu_op(flags.index("N") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"], #W = 0b11101100
        c_qw["F_read_en"] | c_qw["ACU_write_en"],
        alu_op(alu.index("AND")) | c_qw["ACU_write_en"],

        sr_write(sr.index("Z")) | c_qw["TMP_write_en"],
        alu_op(alu.index("OR")) | c_qw["F_write_en"]| c_qw["reset_m_state"] | c_qw["reset_context"]
    ]
}

z = 7
y = 3
instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
   "name": "RRA",
   "subins": [
        mr_read(r.index("A")) | c_qw["TMP_write_en"],
        alu_op(rot.index("RR"),alu_dev.index("SLU"))| mr_write(r.index("A")),

        c_qw["Flatch_read_en"] | c_qw["ACU_write_en"],
        clear_tmp,
        alu_op(flags.index("C") | bit["SET"],alu_dev.index("BMU")) | c_qw["TMP_write_en"],
        alu_op(alu.index("AND")) | sr_write(sr.index("Z")), # Z = 0b0000000C

        internal_byte_to_db(internal_byte.index("FF")) | c_qw["TMP_write_en"],
        alu_op(flags.index("C") | bit["RESET"],alu_dev.index("BMU")) | c_qw["TMP_write_en"],
        alu_op(flags.index("H") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
        alu_op(flags.index("N") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"], #W = 0b11101100
        c_qw["F_read_en"] | c_qw["ACU_write_en"],
        alu_op(alu.index("AND")) | c_qw["ACU_write_en"],

        sr_write(sr.index("Z")) | c_qw["TMP_write_en"],
        alu_op(alu.index("OR")) | c_qw["F_write_en"] | c_qw["reset_m_state"] | c_qw["reset_context"]
    ]
}

z = 7
y = 4
instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
   "name": "DAA",
   "subins": [
        f_to_flatch,
        a_to_acu,
        alu_op(0,alu_dev.index("DAA")) | mr_write(r.index("A")),
        flatch_to_f | c_qw["reset_m_state"] | c_qw["reset_context"]
    ]
}

z = 7
y = 5
instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
   "name": "CPL",
   "subins": [
        a_to_acu,
        alu_op(alu.index("NOT"),save_flags=False) | mr_write(r.index("A")),
        f_to_tmp,
        alu_op(flags.index("H") | bit["SET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
        alu_op(flags.index("N") | bit["SET"],alu_dev.index("BMU"),False) | c_qw["F_write_en"] | c_qw["reset_m_state"] | c_qw["reset_context"]
    ]
}

z = 7
y = 6
instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
   "name": "SCF",
   "subins": [
        f_to_tmp,
        alu_op(flags.index("C") | bit["SET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
        alu_op(flags.index("H") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
        alu_op(flags.index("N") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["F_write_en"] | c_qw["reset_m_state"] | c_qw["reset_context"]
    ]
}

z = 7
y = 7
instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
   "name": "CCF",
   "subins": [
        f_to_acu,
        clear_tmp,
        alu_op(flags.index("C") | bit["SET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
        alu_op(flags.index("H") | bit["SET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
        alu_op(alu.index("XOR"),save_flags=False) | c_qw["TMP_write_en"],
        alu_op(flags.index("N") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["F_write_en"] | c_qw["reset_m_state"] | c_qw["reset_context"]
    ]
}