icaema
/
tc-ucode-generator
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
tc-ucode-generator/quadrants/ed.py

633 lines
25 KiB
Python
Raw Permalink Blame History

from z80shortcuts import *
instructions = [None] * 256
x=1
z=0
for y in range(8):
if y == 6: continue
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"IN {r[y]}, (C)",
"subins": [
clear_acu,
c_qw["Flatch_read_en"] | c_qw["ACU_write_en"],
alu_op(flags.index("C") | bit["SET"],alu_dev.index("BMU")) | c_qw["TMP_write_en"],
alu_op(alu.index("AND")) | sr_write(sr.index("W")), # Z = 0b0000000C
clear_tmp,
mr_read(r.index("C")) | sr_write(sr.index("Z")),
sr_read(sr.index("WZ")) | io_read | c_qw["ACU_write_en"],
alu_op(0,use_overflow=False) | mr_write(y),
c_qw["Flatch_read_en"] | c_qw["TMP_write_en"],
alu_op(flags.index("C") | bit["RESET"],alu_dev.index("BMU"),save_flags=False) | c_qw["TMP_write_en"],
sr_read(sr.index("W")) | c_qw["ACU_write_en"],
alu_op(alu.index("OR"),0,save_flags=False) | c_qw["F_write_en"] | c_qw["reset_context"] | c_qw["reset_m_state"]
]
}
x=1
z=0
y=6
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"IN (C)",
"subins": [
clear_acu,
c_qw["Flatch_read_en"] | c_qw["ACU_write_en"],
alu_op(flags.index("C") | bit["SET"],alu_dev.index("BMU")) | c_qw["TMP_write_en"],
alu_op(alu.index("AND")) | sr_write(sr.index("Z")), # Z = 0b0000000C
clear_tmp,
sr_read(sr.index("Z")) | io_read | c_qw["ACU_write_en"],
alu_op(0,use_overflow=False) | mr_write(r.index("A")),
c_qw["Flatch_read_en"] | c_qw["TMP_write_en"],
alu_op(flags.index("C") | bit["RESET"],alu_dev.index("BMU"),save_flags=False) | c_qw["TMP_write_en"],
sr_read(sr.index("Z")) | c_qw["ACU_write_en"],
alu_op(alu.index("OR"),0,save_flags=False) | c_qw["F_write_en"] | c_qw["reset_context"] | c_qw["reset_m_state"]
]
}
x=1
z=1
for y in range(8):
if y == 6: continue
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"OUT (C), {r[y]}",
"subins": [
sr_write(sr.index("W")), # clear W reg (unneeded for super optimization)
mr_read(r.index("C")) | sr_write(sr.index("Z")),
sr_read(sr.index("WZ")) | mr_read(y) | io_write | c_qw["reset_context"] | c_qw["reset_m_state"]
]
}
x=1
z=1
y=6
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"OUT (C)",
"subins": [
sr_write(sr.index("W")), # clear W reg (unneeded for super optimization)
mr_read(r.index("C")) | sr_write(sr.index("Z")),
sr_read(sr.index("WZ")) | mr_read(r.index("A")) | io_write | c_qw["reset_context"] | c_qw["reset_m_state"]
]
}
x=1
z = 2
q = 0
for p in range(3):
instructions[int(f"0b{x:02b}{((p<<1)+q):03b}{z:03b}", 2)] = {
"name": f"SBC HL, {rp[p]}",
"subins": [
f_to_flatch,
mr_read(r.index("L")) | c_qw["ACU_write_en"],
mr_read((p<<1)+1) | c_qw["TMP_write_en"],
alu_op(alu.index("SBC")) | mr_write(r.index("L")),
mr_read(r.index("H")) | c_qw["ACU_write_en"],
mr_read((p<<1)) | c_qw["TMP_write_en"],
alu_op(alu.index("SBC")) | mr_write(r.index("H")),
flatch_to_f | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=1
z = 2
p = rp.index("SP")
q = 0
instructions[int(f"0b{x:02b}{((p<<1)+q):03b}{z:03b}", 2)] = {
"name": f"SBC HL, SP",
"subins": [
f_to_flatch,
mr_read(r.index("H")) | c_qw["ACU_write_en"],
sr_read(sr.index("SPL")) | c_qw["TMP_write_en"],
alu_op(alu.index("SBC")) | mr_write(r.index("L")),
mr_read(r.index("H")) | c_qw["ACU_write_en"],
sr_read(sr.index("SPH")) | c_qw["TMP_write_en"],
alu_op(alu.index("SBC")) | mr_write(r.index("H")),
flatch_to_f | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=1
z = 2
q = 1
for p in range(3):
instructions[int(f"0b{x:02b}{((p<<1)+q):03b}{z:03b}", 2)] = {
"name": f"ADC HL, {rp[p]}",
"subins": [
f_to_flatch,
mr_read(r.index("L")) | c_qw["ACU_write_en"],
mr_read((p<<1)+1) | c_qw["TMP_write_en"],
alu_op(alu.index("ADC")) | mr_write(r.index("L")),
mr_read(r.index("H")) | c_qw["ACU_write_en"],
mr_read((p<<1)) | c_qw["TMP_write_en"],
alu_op(alu.index("ADC")) | mr_write(r.index("H")),
flatch_to_f | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=1
z = 2
p = rp.index("SP")
q = 1
instructions[int(f"0b{x:02b}{((p<<1)+q):03b}{z:03b}", 2)] = {
"name": f"ADC HL, SP",
"subins": [
f_to_flatch,
mr_read(r.index("H")) | c_qw["ACU_write_en"],
sr_read(sr.index("SPL")) | c_qw["TMP_write_en"],
alu_op(alu.index("ADC")) | mr_write(r.index("L")),
mr_read(r.index("H")) | c_qw["ACU_write_en"],
sr_read(sr.index("SPH")) | c_qw["TMP_write_en"],
alu_op(alu.index("ADC")) | mr_write(r.index("H")),
flatch_to_f | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=1
z = 3
q = 0
for p in range(3):
instructions[int(f"0b{x:02b}{((p<<1)+q):03b}{z:03b}", 2)] = {
"name": f"LD (nn), {rp[p]}",
"subins": [
sr_read(sr.index("PC")) | mem_read | sr_write(sr.index("Z")),
sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
sr_read(sr.index("PC")) | mem_read | sr_write(sr.index("W")),
sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
sr_read(sr.index("WZ")) | mr_read((p<<1)+1) | mem_write | c_qw["addr_inc_en"] | sr_write(sr.index("WZ")),
sr_read(sr.index("WZ")) | mr_read(p<<1) | mem_write | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=1
z = 3
p = rp.index("SP")
q = 0
instructions[int(f"0b{x:02b}{((p<<1)+q):03b}{z:03b}", 2)] = {
"name": f"LD (nn), SP",
"subins": [
sr_read(sr.index("PC")) | mem_read | sr_write(sr.index("Z")),
sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
sr_read(sr.index("PC")) | mem_read | sr_write(sr.index("W")),
sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
sr_read(sr.index("SPL")) | c_qw["TMP_write_en"],
sr_read(sr.index("WZ")) | tmp_to_db | mem_write | c_qw["addr_inc_en"] | sr_write(sr.index("WZ")),
sr_read(sr.index("SPH")) | c_qw["TMP_write_en"],
sr_read(sr.index("WZ")) | tmp_to_db | mem_write | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=1
z = 3
q = 1
for p in range(3):
instructions[int(f"0b{x:02b}{((p<<1)+q):03b}{z:03b}", 2)] = {
"name": f"LD {rp[p]}, (nn)",
"subins": [
sr_read(sr.index("PC")) | mem_read |sr_write(sr.index("Z")),
sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
sr_read(sr.index("PC")) | mem_read | sr_write(sr.index("W")),
sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
sr_read(sr.index("WZ")) | mem_read | mr_write((p<<1)+1),
sr_read(sr.index("WZ")) | c_qw["addr_inc_en"] | sr_write(sr.index("WZ")),
sr_read(sr.index("WZ")) | mem_read | mr_write(p<<1) | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=1
z = 3
p = rp.index("SP")
q = 1
instructions[int(f"0b{x:02b}{((p<<1)+q):03b}{z:03b}", 2)] = {
"name": f"LD SP, (nn)",
"subins": [
sr_read(sr.index("PC")) | mem_read |sr_write(sr.index("Z")),
sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
sr_read(sr.index("PC")) | mem_read | sr_write(sr.index("W")),
sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
sr_read(sr.index("WZ")) | mem_read | sr_write(sr.index("SPL")),
sr_read(sr.index("WZ")) | c_qw["addr_inc_en"] | sr_write(sr.index("WZ")),
sr_read(sr.index("WZ")) | mem_read | sr_write(sr.index("SPH")) | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=1
z=4
for y in range(8):
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"NEG",
"subins": [
clear_acu,
mr_read(r.index("A")) | c_qw["TMP_write_en"],
alu_op(alu.index("SUB")) | mr_write(r.index("A")),
flatch_to_f | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=1
z=5
for y in range(8):
if y == 1: continue
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"RETN",
"subins": [
c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=1
z=5
y=1
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"RETI",
"subins": [
c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=1
z=6
for y in range(8):
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"IM",
"subins": [
c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=1
z=5
y=1
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"RETI",
"subins": [
c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=1
z=5
for y in range(8):
if y in (4, 5): continue
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"NOP",
"subins": [
c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=1
z=5
y=4
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"RRD",
"subins": [
a_to_acu,
mr_read(r.index("(HL)")) | mem_read | c_qw["TMP_write_en"],
alu_op(rot.index("RRD"),alu_dev.index("SLU")) | mr_read(r.index("(HL)")) | mem_write,
alu_op(rot.index("RRD"),alu_dev.index("SLUA"),save_flags=False) | mr_write(r.index("A")),
flatch_to_f | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=1
z=5
y=5
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"RLD",
"subins": [
a_to_acu,
mr_read(r.index("(HL)")) | mem_read | c_qw["TMP_write_en"],
alu_op(rot.index("RLD"),alu_dev.index("SLU")) | mr_read(r.index("(HL)")) | mem_write,
alu_op(rot.index("RLD"),alu_dev.index("SLUA"),save_flags=False) | mr_write(r.index("A")),
flatch_to_f | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=2
y=4
z=0
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"LDI",
"subins": [
clear_acu,
mr_read(r.index("E")) | sr_write(sr.index("Z")),
mr_read(r.index("D")) | sr_write(sr.index("W")),
mr_read(r.index("(HL)")) | mem_read | c_qw["TMP_write_en"],
sr_read(sr.index("WZ")) | tmp_to_db | mem_write,
mr_read(r.index("E")) | c_qw["TMP_write_en"],
alu_op(inc.index("INC"),alu_dev.index("INC")) | mr_write(r.index("E")),
mr_read(r.index("D")) | c_qw["TMP_write_en"],
alu_op(alu.index("ADC")) | mr_write(r.index("D")),
mr_read(r.index("L")) | c_qw["TMP_write_en"],
alu_op(inc.index("INC"),alu_dev.index("INC")) | mr_write(r.index("L")),
mr_read(r.index("H")) | c_qw["TMP_write_en"],
alu_op(alu.index("ADC")) | mr_write(r.index("H")),
mr_read(r.index("C")) | c_qw["TMP_write_en"],
alu_op(inc.index("DEC"),alu_dev.index("INC")) | mr_write(r.index("C")),
clear_tmp,
mr_read(r.index("B")) | c_qw["ACU_write_en"],
alu_op(alu.index("SBC")) | mr_write(r.index("B")),
nop,
exec_if_cond(cc.index("Z")) | mr_read(r.index("C")) | c_qw["TMP_write_en"],
exec_if_cond(cc.index("Z")) | alu_op(0,alu_dev.index("INC")),
f_to_tmp,
alu_op(flags.index("P/V") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
alu_op(flags.index("N") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
alu_op(flags.index("H") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
exec_if_cond(cc.index("Z")) | alu_op(flags.index("P/V") | bit["SET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
tmp_to_db | c_qw["F_write_en"] | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=2
y=5
z=0
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"LDD",
"subins": [
clear_acu,
mr_read(r.index("E")) | sr_write(sr.index("Z")),
mr_read(r.index("D")) | sr_write(sr.index("W")),
mr_read(r.index("(HL)")) | mem_read | c_qw["TMP_write_en"],
sr_read(sr.index("WZ")) | tmp_to_db | mem_write,
mr_read(r.index("E")) | c_qw["TMP_write_en"],
alu_op(inc.index("DEC"),alu_dev.index("INC")) | mr_write(r.index("E")),
clear_tmp,
mr_read(r.index("D")) | c_qw["ACU_write_en"],
alu_op(alu.index("SBC")) | mr_write(r.index("D")),
mr_read(r.index("L")) | c_qw["TMP_write_en"],
alu_op(inc.index("DEC"),alu_dev.index("INC")) | mr_write(r.index("L")),
clear_tmp,
mr_read(r.index("H")) | c_qw["ACU_write_en"],
alu_op(alu.index("SBC")) | mr_write(r.index("H")),
mr_read(r.index("C")) | c_qw["TMP_write_en"],
alu_op(inc.index("DEC"),alu_dev.index("INC")) | mr_write(r.index("C")),
clear_tmp,
mr_read(r.index("B")) | c_qw["ACU_write_en"],
alu_op(alu.index("SBC")) | mr_write(r.index("B")),
nop,
exec_if_cond(cc.index("Z")) | mr_read(r.index("C")) | c_qw["TMP_write_en"],
exec_if_cond(cc.index("Z")) | alu_op(0,alu_dev.index("INC")),
f_to_tmp,
alu_op(flags.index("P/V") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
alu_op(flags.index("N") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
alu_op(flags.index("H") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
exec_if_cond(cc.index("Z")) | alu_op(flags.index("P/V") | bit["SET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
tmp_to_db | c_qw["F_write_en"] | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=2
y=6
z=0
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"LDIR",
"subins": [
clear_acu,
mr_read(r.index("E")) | sr_write(sr.index("Z")),
mr_read(r.index("D")) | sr_write(sr.index("W")),
mr_read(r.index("(HL)")) | mem_read | c_qw["TMP_write_en"],
sr_read(sr.index("WZ")) | tmp_to_db | mem_write,
mr_read(r.index("E")) | c_qw["TMP_write_en"],
alu_op(inc.index("INC"),alu_dev.index("INC")) | mr_write(r.index("E")),
mr_read(r.index("D")) | c_qw["TMP_write_en"],
alu_op(alu.index("ADC")) | mr_write(r.index("D")),
mr_read(r.index("L")) | c_qw["TMP_write_en"],
alu_op(inc.index("INC"),alu_dev.index("INC")) | mr_write(r.index("L")),
mr_read(r.index("H")) | c_qw["TMP_write_en"],
alu_op(alu.index("ADC")) | mr_write(r.index("H")),
mr_read(r.index("C")) | c_qw["TMP_write_en"],
alu_op(inc.index("DEC"),alu_dev.index("INC")) | mr_write(r.index("C")),
clear_tmp,
mr_read(r.index("B")) | c_qw["ACU_write_en"],
alu_op(alu.index("SBC")) | mr_write(r.index("B")),
nop,
exec_if_cond(cc.index("Z")) | mr_read(r.index("C")) | c_qw["TMP_write_en"],
exec_if_cond(cc.index("Z")) | alu_op(0,alu_dev.index("INC")),
nop,
exec_if_cond(cc.index("NZ")) | sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | c_qw["addr_dec"] | sr_write(sr.index("PC")),
exec_if_cond(cc.index("NZ")) | sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | c_qw["addr_dec"] | sr_write(sr.index("PC")),
f_to_tmp,
alu_op(flags.index("P/V") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
alu_op(flags.index("N") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
alu_op(flags.index("H") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
exec_if_cond(cc.index("Z")) | alu_op(flags.index("P/V") | bit["SET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
tmp_to_db | c_qw["F_write_en"],
c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=2
y=7
z=0
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"LDDR",
"subins": [
clear_acu,
mr_read(r.index("E")) | sr_write(sr.index("Z")),
mr_read(r.index("D")) | sr_write(sr.index("W")),
mr_read(r.index("(HL)")) | mem_read | c_qw["TMP_write_en"],
sr_read(sr.index("WZ")) | tmp_to_db | mem_write,
mr_read(r.index("E")) | c_qw["TMP_write_en"],
alu_op(inc.index("DEC"),alu_dev.index("INC")) | mr_write(r.index("E")),
clear_tmp,
mr_read(r.index("D")) | c_qw["ACU_write_en"],
alu_op(alu.index("SBC")) | mr_write(r.index("D")),
mr_read(r.index("L")) | c_qw["TMP_write_en"],
alu_op(inc.index("DEC"),alu_dev.index("INC")) | mr_write(r.index("L")),
clear_tmp,
mr_read(r.index("H")) | c_qw["ACU_write_en"],
alu_op(alu.index("SBC")) | mr_write(r.index("H")),
mr_read(r.index("C")) | c_qw["TMP_write_en"],
alu_op(inc.index("DEC"),alu_dev.index("INC")) | mr_write(r.index("C")),
clear_tmp,
mr_read(r.index("B")) | c_qw["ACU_write_en"],
alu_op(alu.index("SBC")) | mr_write(r.index("B")),
nop,
exec_if_cond(cc.index("Z")) | mr_read(r.index("C")) | c_qw["TMP_write_en"],
exec_if_cond(cc.index("Z")) | alu_op(0,alu_dev.index("INC")),
nop,
exec_if_cond(cc.index("NZ")) | sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | c_qw["addr_dec"] | sr_write(sr.index("PC")),
exec_if_cond(cc.index("NZ")) | sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | c_qw["addr_dec"] | sr_write(sr.index("PC")),
f_to_tmp,
alu_op(flags.index("P/V") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
alu_op(flags.index("N") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
alu_op(flags.index("H") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
exec_if_cond(cc.index("Z")) | alu_op(flags.index("P/V") | bit["SET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
tmp_to_db | c_qw["F_write_en"] | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=2
y=4
z=1
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"CPI",
"subins": [
a_to_acu,
mr_read(r.index("(HL)")) | mem_read | c_qw["TMP_write_en"],
alu_op(alu.index("SUB")),
flatch_to_f,
mr_read(r.index("L")) | c_qw["TMP_write_en"],
alu_op(inc.index("INC"),alu_dev.index("INC")) | mr_write(r.index("L")),
mr_read(r.index("H")) | c_qw["TMP_write_en"],
alu_op(alu.index("ADC")) | mr_write(r.index("H")),
mr_read(r.index("C")) | c_qw["TMP_write_en"],
alu_op(inc.index("DEC"),alu_dev.index("INC")) | mr_write(r.index("C")),
clear_tmp,
mr_read(r.index("B")) | c_qw["ACU_write_en"],
alu_op(alu.index("SBC")) | mr_write(r.index("B")),
f_to_tmp,
alu_op(flags.index("P/V") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
exec_if_cond(cc.index("Z")) | alu_op(flags.index("P/V") | bit["SET"],alu_dev.index("BMU"),False) | c_qw["F_write_en"] | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=2
y=5
z=1
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"CPD",
"subins": [
a_to_acu,
mr_read(r.index("(HL)")) | mem_read | c_qw["TMP_write_en"],
alu_op(alu.index("SUB")),
flatch_to_f,
mr_read(r.index("L")) | c_qw["TMP_write_en"],
alu_op(inc.index("DEC"),alu_dev.index("INC")) | mr_write(r.index("L")),
clear_tmp,
mr_read(r.index("H")) | c_qw["ACU_write_en"],
alu_op(alu.index("SBC")) | mr_write(r.index("H")),
mr_read(r.index("C")) | c_qw["TMP_write_en"],
alu_op(inc.index("DEC"),alu_dev.index("INC")) | mr_write(r.index("C")),
clear_tmp,
mr_read(r.index("B")) | c_qw["ACU_write_en"],
alu_op(alu.index("SBC")) | mr_write(r.index("B")),
f_to_tmp,
alu_op(flags.index("P/V") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
exec_if_cond(cc.index("Z")) | alu_op(flags.index("P/V") | bit["SET"],alu_dev.index("BMU"),False) | c_qw["F_write_en"] | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=2
y=6
z=1
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"CPIR",
"subins": [
a_to_acu,
mr_read(r.index("(HL)")) | mem_read | c_qw["TMP_write_en"],
alu_op(alu.index("SUB")),
flatch_to_f,
mr_read(r.index("L")) | c_qw["TMP_write_en"],
alu_op(inc.index("INC"),alu_dev.index("INC")) | mr_write(r.index("L")),
mr_read(r.index("H")) | c_qw["TMP_write_en"],
alu_op(alu.index("ADC")) | mr_write(r.index("H")),
mr_read(r.index("C")) | c_qw["TMP_write_en"],
alu_op(inc.index("DEC"),alu_dev.index("INC")) | mr_write(r.index("C")),
clear_tmp,
mr_read(r.index("B")) | c_qw["ACU_write_en"],
alu_op(alu.index("SBC")) | mr_write(r.index("B")),
f_to_tmp,
alu_op(flags.index("P/V") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
exec_if_cond(cc.index("Z")) | alu_op(flags.index("P/V") | bit["SET"],alu_dev.index("BMU"),False) | c_qw["F_write_en"],
f_to_flatch,
nop,
exec_if_cond(cc.index("PE")) | sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | c_qw["addr_dec"] | sr_write(sr.index("PC")),
exec_if_cond(cc.index("PE")) | sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | c_qw["addr_dec"] | sr_write(sr.index("PC")) | c_qw["reset_m_state"] | c_qw["reset_context"],
exec_if_cond(cc.index("NZ")) | sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | c_qw["addr_dec"] | sr_write(sr.index("PC")),
exec_if_cond(cc.index("NZ")) | sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | c_qw["addr_dec"] | sr_write(sr.index("PC")) | c_qw["reset_m_state"] | c_qw["reset_context"],
c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=2
y=7
z=1
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"CPDR",
"subins": [
clear_acu,
mr_read(r.index("(HL)")) | mem_read | c_qw["TMP_write_en"],
alu_op(alu.index("SUB")),
flatch_to_f,
mr_read(r.index("L")) | c_qw["TMP_write_en"],
alu_op(inc.index("DEC"),alu_dev.index("INC")) | mr_write(r.index("L")),
clear_tmp,
mr_read(r.index("H")) | c_qw["ACU_write_en"],
alu_op(alu.index("SBC")) | mr_write(r.index("H")),
mr_read(r.index("C")) | c_qw["TMP_write_en"],
alu_op(inc.index("DEC"),alu_dev.index("INC")) | mr_write(r.index("C")),
clear_tmp,
mr_read(r.index("B")) | c_qw["ACU_write_en"],
alu_op(alu.index("SBC")) | mr_write(r.index("B")),
f_to_tmp,
alu_op(flags.index("P/V") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
exec_if_cond(cc.index("Z")) | alu_op(flags.index("P/V") | bit["SET"],alu_dev.index("BMU"),False) | c_qw["F_write_en"],
f_to_flatch,
nop,
exec_if_cond(cc.index("PE")) | sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | c_qw["addr_dec"] | sr_write(sr.index("PC")),
exec_if_cond(cc.index("PE")) | sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | c_qw["addr_dec"] | sr_write(sr.index("PC")) | c_qw["reset_m_state"] | c_qw["reset_context"],
exec_if_cond(cc.index("NZ")) | sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | c_qw["addr_dec"] | sr_write(sr.index("PC")),
exec_if_cond(cc.index("NZ")) | sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | c_qw["addr_dec"] | sr_write(sr.index("PC")) | c_qw["reset_m_state"] | c_qw["reset_context"],
c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=2
y=4
z=2
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"INI",
"subins": [
clear_acu,
mr_read(r.index("C")) | sr_write(sr.index("Z")),
sr_read(sr.index("WZ")) | io_read | c_qw["TMP_write_en"],
mr_read(r.index("(HL)")) | tmp_to_db | mem_write,
mr_read(r.index("L")) | c_qw["TMP_write_en"],
alu_op(inc.index("INC"),alu_dev.index("INC")) | mr_write(r.index("L")),
mr_read(r.index("H")) | c_qw["TMP_write_en"],
alu_op(alu.index("ADC")) | mr_write(r.index("H")),
c_qw["Flatch_read_en"] | c_qw["ACU_write_en"],
alu_op(flags.index("C") | bit["SET"],alu_dev.index("BMU")) | c_qw["TMP_write_en"],
alu_op(alu.index("AND")) | sr_write(sr.index("Z")), # Z = 0b0000000C
mr_read(r.index("B")) | c_qw["TMP_write_en"],
alu_op(inc.index("DEC"),alu_dev.index("INC")) | mr_write(r.index("B")),
f_to_tmp,
alu_op(flags.index("Z") | bit["RESET"],alu_dev.index("BMU"),save_flags=False) | c_qw["TMP_write_en"],
alu_op(flags.index("C") | bit["RESET"],alu_dev.index("BMU"),save_flags=False) | c_qw["TMP_write_en"],
sr_read(sr.index("Z")) | c_qw["ACU_write_en"],
alu_op(alu.index("OR"),0,save_flags=False) | c_qw["TMP_write_en"],
exec_if_cond(cc.index("Z")) | alu_op(flags.index("Z") | bit["SET"],alu_dev.index("BMU"),False) | c_qw["F_write_en"],
f_to_flatch | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
Reference in New Issue View Git Blame Copy Permalink