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tc-ucode-generator/quadrants/cb.py

163 lines
7.4 KiB
Python
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from z80shortcuts import *
instructions = [None] * 256
x=0
for y in range(8):
for z in range(8):
if z == r.index("(HL)"): continue
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"{rot[y]} {r[z]}",
"subins": [
f_to_flatch,
mr_read(z) | c_qw["TMP_write_en"],
alu_op(y,alu_dev.index("SLU"),use_overflow=False) | mr_write(z),
flatch_to_f | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=0
z=r.index("(HL)")
for y in range(8):
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"{rot[y]} {r[z]}",
"subins": [
exec_if_context | sr_read(sr.index("PC")) | mem_read | c_qw["ACU_write_en"] | c_qw["TMP_write_en"] | sr_write(sr.index("Z")),
exec_if_context | sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
#sign extend
exec_if_context | alu_op(alu.index("ADD")),
exec_if_context | alu_op(alu.index("SBC")) | sr_write(sr.index("W")),
exec_if_context | mr_read(r.index("L")) | c_qw["ACU_write_en"],
exec_if_context | sr_read(sr.index("Z")) | c_qw["TMP_write_en"],
exec_if_context | alu_op(alu.index("ADD")) | sr_write(sr.index("Z")),
exec_if_context | mr_read(r.index("H")) | c_qw["ACU_write_en"],
exec_if_context | sr_read(sr.index("W")) | c_qw["TMP_write_en"],
exec_if_context | alu_op(alu.index("ADC")) | sr_write(sr.index("W")),
f_to_flatch,
mr_read(r.index("(HL)")) | mem_read | c_qw["TMP_write_en"],
alu_op(y,alu_dev.index("SLU"),use_overflow=False) | mr_read(r.index("(HL)")) | mem_write,
flatch_to_f | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=1
for y in range(8):
for z in range(8):
if z == r.index("(HL)"): continue
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"BIT {y} {r[z]}",
"subins": [
f_to_flatch,
mr_read(z) | c_qw["TMP_write_en"],
alu_op(y,alu_dev.index("BMU"),use_overflow=False) | mr_write(z),
flatch_to_f | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=1
z=r.index("(HL)")
for y in range(8):
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"BIT {y} {r[z]}",
"subins": [
exec_if_context | sr_read(sr.index("PC")) | mem_read | c_qw["ACU_write_en"] | c_qw["TMP_write_en"] | sr_write(sr.index("Z")),
exec_if_context | sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
#sign extend
exec_if_context | alu_op(alu.index("ADD")),
exec_if_context | alu_op(alu.index("SBC")) | sr_write(sr.index("W")),
exec_if_context | mr_read(r.index("L")) | c_qw["ACU_write_en"],
exec_if_context | sr_read(sr.index("Z")) | c_qw["TMP_write_en"],
exec_if_context | alu_op(alu.index("ADD")) | sr_write(sr.index("Z")),
exec_if_context | mr_read(r.index("H")) | c_qw["ACU_write_en"],
exec_if_context | sr_read(sr.index("W")) | c_qw["TMP_write_en"],
exec_if_context | alu_op(alu.index("ADC")) | sr_write(sr.index("W")),
f_to_flatch,
mr_read(r.index("(HL)")) | mem_read | c_qw["TMP_write_en"],
alu_op(y,alu_dev.index("BMU"),use_overflow=False) | mr_read(r.index("(HL)")) | mem_write,
flatch_to_f | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=2
for y in range(8):
for z in range(8):
if z == r.index("(HL)"): continue
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"RES {y} {r[z]}",
"subins": [
f_to_flatch,
mr_read(z) | c_qw["TMP_write_en"],
alu_op((y|bit["RESET"]),alu_dev.index("BMU"),use_overflow=False) | mr_write(z),
flatch_to_f | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=2
z=r.index("(HL)")
for y in range(8):
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"RES {y} {r[z]}",
"subins": [
exec_if_context | sr_read(sr.index("PC")) | mem_read | c_qw["ACU_write_en"] | c_qw["TMP_write_en"] | sr_write(sr.index("Z")),
exec_if_context | sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
#sign extend
exec_if_context | alu_op(alu.index("ADD")),
exec_if_context | alu_op(alu.index("SBC")) | sr_write(sr.index("W")),
exec_if_context | mr_read(r.index("L")) | c_qw["ACU_write_en"],
exec_if_context | sr_read(sr.index("Z")) | c_qw["TMP_write_en"],
exec_if_context | alu_op(alu.index("ADD")) | sr_write(sr.index("Z")),
exec_if_context | mr_read(r.index("H")) | c_qw["ACU_write_en"],
exec_if_context | sr_read(sr.index("W")) | c_qw["TMP_write_en"],
exec_if_context | alu_op(alu.index("ADC")) | sr_write(sr.index("W")),
f_to_flatch,
mr_read(r.index("(HL)")) | mem_read | c_qw["TMP_write_en"],
alu_op((y|bit["RESET"]),alu_dev.index("BMU"),use_overflow=False) | mr_read(r.index("(HL)")) | mem_write,
flatch_to_f | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=3
for y in range(8):
for z in range(8):
if z == r.index("(HL)"): continue
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"SET {y} {r[z]}",
"subins": [
f_to_flatch,
mr_read(z) | c_qw["TMP_write_en"],
alu_op((y|bit["SET"]),alu_dev.index("BMU"),use_overflow=False) | mr_write(z),
flatch_to_f | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=3
z=r.index("(HL)")
for y in range(8):
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"SET {y} {r[z]}",
"subins": [
exec_if_context | sr_read(sr.index("PC")) | mem_read | c_qw["ACU_write_en"] | c_qw["TMP_write_en"] | sr_write(sr.index("Z")),
exec_if_context | sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
#sign extend
exec_if_context | alu_op(alu.index("ADD")),
exec_if_context | alu_op(alu.index("SBC")) | sr_write(sr.index("W")),
exec_if_context | mr_read(r.index("L")) | c_qw["ACU_write_en"],
exec_if_context | sr_read(sr.index("Z")) | c_qw["TMP_write_en"],
exec_if_context | alu_op(alu.index("ADD")) | sr_write(sr.index("Z")),
exec_if_context | mr_read(r.index("H")) | c_qw["ACU_write_en"],
exec_if_context | sr_read(sr.index("W")) | c_qw["TMP_write_en"],
exec_if_context | alu_op(alu.index("ADC")) | sr_write(sr.index("W")),
f_to_flatch,
mr_read(r.index("(HL)")) | mem_read | c_qw["TMP_write_en"],
alu_op((y|bit["SET"]),alu_dev.index("BMU"),use_overflow=False) | mr_read(r.index("(HL)")) | mem_write,
flatch_to_f | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
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