icaema
/
tc-z80-ucode-generator
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

add to git

This commit is contained in:
icaema 2022-12-20 20:41:36 -05:00
commit 2bff740a92
13 changed files with 2828 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
.gitignore vendored Normal file
View File

@ -0,0 +1 @@
__pycache__

5
checker.sh Normal file
View File

@ -0,0 +1,5 @@
#!/bin/bash
cat z80opcodelist.txt | tr -s ' ' | awk -F ' ' '{{printf "0x%s %s",$1,$2;} if ($3!="-"){printf " "$3} printf "\n"}' | \
sed -r -e 's/,/, /' -e 's/&0000/nn/' -e 's/&00/n/' -e 's/&4546/d/' -e 's/&[0-9][0-9]//' -e 's/\*\*\*\* //' | perl -pe 's/(?<=[AS][DUB][DBC]) A,//' > z80opcodelist.form.txt
python3 decoder_generator.py -l | grep -v -Ff z80opcodelist.form.txt

182
dec.out Normal file
View File

@ -0,0 +1,182 @@
0x0 NOP
0x1 LD BC,nn
0x2 LD (BC), A
0x3 INC BC
0x4 INC B
0x5 DEC B
0x6 LD B, n
0x8 EX AF,AF'
0x9 ADD HL,BC
0xa LD A, (BC)
0xb DEC BC
0xc INC C
0xd DEC C
0xe LD C, n
0x10 DJNZ d
0x11 LD DE,nn
0x12 LD (DE), A
0x13 INC DE
0x14 INC D
0x15 DEC D
0x16 LD D, n
0x18 JR d
0x19 ADD HL,DE
0x1a LD A, (DE)
0x1b DEC DE
0x1c INC E
0x1d DEC E
0x1e LD E, n
0x20 JR NZ,d
0x21 LD HL,nn
0x22 LD (nn), HL
0x24 INC H
0x25 DEC H
0x26 LD H, n
0x28 JR Z,d
0x29 ADD HL,HL
0x2a LD HL, (nn)
0x2c INC L
0x2d DEC L
0x2e LD L, n
0x30 JR NC,d
0x31 LD SP,nn
0x32 LD (nn), A
0x33 INC SP
0x34 INC (HL)
0x35 DEC (HL)
0x36 LD (HL), n
0x38 JR C,d
0x39 ADD HL,SP
0x3a LD A, (nn)
0x3b DEC SP
0x3c INC A
0x3d DEC A
0x3e LD A, n
0x40 LD B, B
0x41 LD B, C
0x42 LD B, D
0x43 LD B, E
0x44 LD B, H
0x45 LD B, L
0x46 LD B, (HL)
0x47 LD B, A
0x48 LD C, B
0x49 LD C, C
0x4a LD C, D
0x4b LD C, E
0x4c LD C, H
0x4d LD C, L
0x4e LD C, (HL)
0x4f LD C, A
0x50 LD D, B
0x51 LD D, C
0x52 LD D, D
0x53 LD D, E
0x54 LD D, H
0x55 LD D, L
0x56 LD D, (HL)
0x57 LD D, A
0x58 LD E, B
0x59 LD E, C
0x5a LD E, D
0x5b LD E, E
0x5c LD E, H
0x5d LD E, L
0x5e LD E, (HL)
0x5f LD E, A
0x60 LD H, B
0x61 LD H, C
0x62 LD H, D
0x63 LD H, E
0x64 LD H, H
0x65 LD H, L
0x66 LD H, (HL)
0x67 LD H, A
0x68 LD L, B
0x69 LD L, C
0x6a LD L, D
0x6b LD L, E
0x6c LD L, H
0x6d LD L, L
0x6e LD L, (HL)
0x6f LD L, A
0x70 LD (HL), B
0x71 LD (HL), C
0x72 LD (HL), D
0x73 LD (HL), E
0x74 LD (HL), H
0x75 LD (HL), L
0x76 HALT
0x77 LD (HL), A
0x78 LD A, B
0x79 LD A, C
0x7a LD A, D
0x7b LD A, E
0x7c LD A, H
0x7d LD A, L
0x7e LD A, (HL)
0x7f LD A, A
0x80 ADD B
0x81 ADD C
0x82 ADD D
0x83 ADD E
0x84 ADD H
0x85 ADD L
0x86 ADD (HL)
0x87 ADD A
0x88 ADC B
0x89 ADC C
0x8a ADC D
0x8b ADC E
0x8c ADC H
0x8d ADC L
0x8e ADC (HL)
0x8f ADC A
0x90 SUB B
0x91 SUB C
0x92 SUB D
0x93 SUB E
0x94 SUB H
0x95 SUB L
0x96 SUB (HL)
0x97 SUB A
0x98 SBC B
0x99 SBC C
0x9a SBC D
0x9b SBC E
0x9c SBC H
0x9d SBC L
0x9e SBC (HL)
0x9f SBC A
0xa0 AND B
0xa1 AND C
0xa2 AND D
0xa3 AND E
0xa4 AND H
0xa5 AND L
0xa6 AND (HL)
0xa7 AND A
0xa8 XOR B
0xa9 XOR C
0xaa XOR D
0xab XOR E
0xac XOR H
0xad XOR L
0xae XOR (HL)
0xaf XOR A
0xb0 OR B
0xb1 OR C
0xb2 OR D
0xb3 OR E
0xb4 OR H
0xb5 OR L
0xb6 OR (HL)
0xb7 OR A
0xb8 CP B
0xb9 CP C
0xba CP D
0xbb CP E
0xbc CP H
0xbd CP L
0xbe CP (HL)
0xbf CP A

86
decoder_generator.py Normal file
View File

@ -0,0 +1,86 @@
import enum
import sys
import re
import pprint
from z80shortcuts import *
from quadrants.mq0 import instructions as instructions_main_0
from quadrants.mq1 import instructions as instructions_main_1
from quadrants.mq2 import instructions as instructions_main_2
from quadrants.mq3 import instructions as instructions_main_3
from quadrants.cb import instructions as instructions_cb
from quadrants.ed import instructions as instructions_ed
instructions = [None] * 256
# ========== Main Quadrant 0
for i, x in enumerate(instructions_main_0):
if x == None: continue
instructions[i] = x
# ========== Main Quadrant 1
for i, x in enumerate(instructions_main_1):
if x == None: continue
instructions[i] = x
# ========== Main Quadrant 2
for i, x in enumerate(instructions_main_2):
if x == None: continue
instructions[i] = x
# ======== Main Quadrant 3
for i, x in enumerate(instructions_main_3):
if x == None: continue
instructions[i] = x
# =====================================
if __name__ == "__main__":
if len(sys.argv) < 2: exit()
if sys.argv[1] == "-l":
ins_set = instructions
if len(sys.argv) >= 3 and sys.argv[2] == "CB":
ins_set = instructions_cb
if len(sys.argv) >= 3 and sys.argv[2] == "ED":
ins_set = instructions_ed
for i, x in enumerate(ins_set):
if x == None: continue
print(f"0x{i:02X}", x['name'])
if len(x['subins']) > 0:
if len(x['subins']) > 32: print("TOO BIG")
for y in x['subins']:
print(end="")
#print(f"0b{y:064b}", y, f"0x{y:016X}")
elif sys.argv[1] == "-g":
ins_set = instructions
filename = "decoderout_main.rom"
if len(sys.argv) >= 3 and sys.argv[2] == "CB":
ins_set = instructions_cb
filename = "decoderout_CB.rom"
if len(sys.argv) >= 3 and sys.argv[2] == "ED":
ins_set = instructions_ed
filename = "decoderout_ED.rom"
instruction_subins_in_printable_order = [b'\x00'] *256 *32 *8
for x, instruction in enumerate(ins_set):
if instruction == None: continue
subins_template_list = [b'\x00'] *8 *32
for i, subin in enumerate(instruction['subins']):
subin_bytes_hex = re.findall(r'..', f"{subin:016X}")
subin_bytes_hex.reverse()
for j, by in enumerate(subin_bytes_hex):
subins_template_list[i*8+j] = bytes.fromhex(by)
for i, by in enumerate(subins_template_list):
#print(by)
instruction_subins_in_printable_order[(x*8*32)+i] = by
#print(instruction_subins_in_printable_order)
with open(filename, 'wb+') as out_file:
for x in instruction_subins_in_printable_order:
out_file.write(x)

163
quadrants/cb.py Normal file
View File

@ -0,0 +1,163 @@
from z80shortcuts import *
instructions = [None] * 256
x=0
for y in range(8):
for z in range(8):
if z == r.index("(HL)"): continue
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"{rot[y]} {r[z]}",
"subins": [
f_to_flatch,
mr_read(z) | c_qw["TMP_write_en"],
alu_op(y,alu_dev.index("SLU"),use_overflow=False) | mr_write(z),
flatch_to_f | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=0
z=r.index("(HL)")
for y in range(8):
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"{rot[y]} {r[z]}",
"subins": [
exec_if_context | sr_read(sr.index("PC")) | mem_read | c_qw["ACU_write_en"] | c_qw["TMP_write_en"] | sr_write(sr.index("Z")),
exec_if_context | sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
#sign extend
exec_if_context | alu_op(alu.index("ADD")),
exec_if_context | alu_op(alu.index("SBC")) | sr_write(sr.index("W")),
exec_if_context | mr_read(r.index("L")) | c_qw["ACU_write_en"],
exec_if_context | sr_read(sr.index("Z")) | c_qw["TMP_write_en"],
exec_if_context | alu_op(alu.index("ADD")) | sr_write(sr.index("Z")),
exec_if_context | mr_read(r.index("H")) | c_qw["ACU_write_en"],
exec_if_context | sr_read(sr.index("W")) | c_qw["TMP_write_en"],
exec_if_context | alu_op(alu.index("ADC")) | sr_write(sr.index("W")),
f_to_flatch,
mr_read(r.index("(HL)")) | mem_read | c_qw["TMP_write_en"],
alu_op(y,alu_dev.index("SLU"),use_overflow=False) | mr_read(r.index("(HL)")) | mem_write,
flatch_to_f | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=1
for y in range(8):
for z in range(8):
if z == r.index("(HL)"): continue
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"BIT {y} {r[z]}",
"subins": [
f_to_flatch,
mr_read(z) | c_qw["TMP_write_en"],
alu_op(y,alu_dev.index("BMU"),use_overflow=False) | mr_write(z),
flatch_to_f | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=1
z=r.index("(HL)")
for y in range(8):
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"BIT {y} {r[z]}",
"subins": [
exec_if_context | sr_read(sr.index("PC")) | mem_read | c_qw["ACU_write_en"] | c_qw["TMP_write_en"] | sr_write(sr.index("Z")),
exec_if_context | sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
#sign extend
exec_if_context | alu_op(alu.index("ADD")),
exec_if_context | alu_op(alu.index("SBC")) | sr_write(sr.index("W")),
exec_if_context | mr_read(r.index("L")) | c_qw["ACU_write_en"],
exec_if_context | sr_read(sr.index("Z")) | c_qw["TMP_write_en"],
exec_if_context | alu_op(alu.index("ADD")) | sr_write(sr.index("Z")),
exec_if_context | mr_read(r.index("H")) | c_qw["ACU_write_en"],
exec_if_context | sr_read(sr.index("W")) | c_qw["TMP_write_en"],
exec_if_context | alu_op(alu.index("ADC")) | sr_write(sr.index("W")),
f_to_flatch,
mr_read(r.index("(HL)")) | mem_read | c_qw["TMP_write_en"],
alu_op(y,alu_dev.index("BMU"),use_overflow=False) | mr_read(r.index("(HL)")) | mem_write,
flatch_to_f | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=2
for y in range(8):
for z in range(8):
if z == r.index("(HL)"): continue
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"RES {y} {r[z]}",
"subins": [
f_to_flatch,
mr_read(z) | c_qw["TMP_write_en"],
alu_op((y|bit["RESET"]),alu_dev.index("BMU"),use_overflow=False) | mr_write(z),
flatch_to_f | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=2
z=r.index("(HL)")
for y in range(8):
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"RES {y} {r[z]}",
"subins": [
exec_if_context | sr_read(sr.index("PC")) | mem_read | c_qw["ACU_write_en"] | c_qw["TMP_write_en"] | sr_write(sr.index("Z")),
exec_if_context | sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
#sign extend
exec_if_context | alu_op(alu.index("ADD")),
exec_if_context | alu_op(alu.index("SBC")) | sr_write(sr.index("W")),
exec_if_context | mr_read(r.index("L")) | c_qw["ACU_write_en"],
exec_if_context | sr_read(sr.index("Z")) | c_qw["TMP_write_en"],
exec_if_context | alu_op(alu.index("ADD")) | sr_write(sr.index("Z")),
exec_if_context | mr_read(r.index("H")) | c_qw["ACU_write_en"],
exec_if_context | sr_read(sr.index("W")) | c_qw["TMP_write_en"],
exec_if_context | alu_op(alu.index("ADC")) | sr_write(sr.index("W")),
f_to_flatch,
mr_read(r.index("(HL)")) | mem_read | c_qw["TMP_write_en"],
alu_op((y|bit["RESET"]),alu_dev.index("BMU"),use_overflow=False) | mr_read(r.index("(HL)")) | mem_write,
flatch_to_f | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=3
for y in range(8):
for z in range(8):
if z == r.index("(HL)"): continue
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"SET {y} {r[z]}",
"subins": [
f_to_flatch,
mr_read(z) | c_qw["TMP_write_en"],
alu_op((y|bit["SET"]),alu_dev.index("BMU"),use_overflow=False) | mr_write(z),
flatch_to_f | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=3
z=r.index("(HL)")
for y in range(8):
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"SET {y} {r[z]}",
"subins": [
exec_if_context | sr_read(sr.index("PC")) | mem_read | c_qw["ACU_write_en"] | c_qw["TMP_write_en"] | sr_write(sr.index("Z")),
exec_if_context | sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
#sign extend
exec_if_context | alu_op(alu.index("ADD")),
exec_if_context | alu_op(alu.index("SBC")) | sr_write(sr.index("W")),
exec_if_context | mr_read(r.index("L")) | c_qw["ACU_write_en"],
exec_if_context | sr_read(sr.index("Z")) | c_qw["TMP_write_en"],
exec_if_context | alu_op(alu.index("ADD")) | sr_write(sr.index("Z")),
exec_if_context | mr_read(r.index("H")) | c_qw["ACU_write_en"],
exec_if_context | sr_read(sr.index("W")) | c_qw["TMP_write_en"],
exec_if_context | alu_op(alu.index("ADC")) | sr_write(sr.index("W")),
f_to_flatch,
mr_read(r.index("(HL)")) | mem_read | c_qw["TMP_write_en"],
alu_op((y|bit["SET"]),alu_dev.index("BMU"),use_overflow=False) | mr_read(r.index("(HL)")) | mem_write,
flatch_to_f | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}

633
quadrants/ed.py Normal file
View File

@ -0,0 +1,633 @@
from z80shortcuts import *
instructions = [None] * 256
x=1
z=0
for y in range(8):
if y == 6: continue
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"IN {r[y]}, (C)",
"subins": [
clear_acu,
c_qw["Flatch_read_en"] | c_qw["ACU_write_en"],
alu_op(flags.index("C") | bit["SET"],alu_dev.index("BMU")) | c_qw["TMP_write_en"],
alu_op(alu.index("AND")) | sr_write(sr.index("W")), # Z = 0b0000000C
clear_tmp,
mr_read(r.index("C")) | sr_write(sr.index("Z")),
sr_read(sr.index("WZ")) | io_read | c_qw["ACU_write_en"],
alu_op(0,use_overflow=False) | mr_write(y),
c_qw["Flatch_read_en"] | c_qw["TMP_write_en"],
alu_op(flags.index("C") | bit["RESET"],alu_dev.index("BMU"),save_flags=False) | c_qw["TMP_write_en"],
sr_read(sr.index("W")) | c_qw["ACU_write_en"],
alu_op(alu.index("OR"),0,save_flags=False) | c_qw["F_write_en"] | c_qw["reset_context"] | c_qw["reset_m_state"]
]
}
x=1
z=0
y=6
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"IN (C)",
"subins": [
clear_acu,
c_qw["Flatch_read_en"] | c_qw["ACU_write_en"],
alu_op(flags.index("C") | bit["SET"],alu_dev.index("BMU")) | c_qw["TMP_write_en"],
alu_op(alu.index("AND")) | sr_write(sr.index("Z")), # Z = 0b0000000C
clear_tmp,
sr_read(sr.index("Z")) | io_read | c_qw["ACU_write_en"],
alu_op(0,use_overflow=False) | mr_write(r.index("A")),
c_qw["Flatch_read_en"] | c_qw["TMP_write_en"],
alu_op(flags.index("C") | bit["RESET"],alu_dev.index("BMU"),save_flags=False) | c_qw["TMP_write_en"],
sr_read(sr.index("Z")) | c_qw["ACU_write_en"],
alu_op(alu.index("OR"),0,save_flags=False) | c_qw["F_write_en"] | c_qw["reset_context"] | c_qw["reset_m_state"]
]
}
x=1
z=1
for y in range(8):
if y == 6: continue
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"OUT (C), {r[y]}",
"subins": [
sr_write(sr.index("W")), # clear W reg (unneeded for super optimization)
mr_read(r.index("C")) | sr_write(sr.index("Z")),
sr_read(sr.index("WZ")) | mr_read(y) | io_write | c_qw["reset_context"] | c_qw["reset_m_state"]
]
}
x=1
z=1
y=6
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"OUT (C)",
"subins": [
sr_write(sr.index("W")), # clear W reg (unneeded for super optimization)
mr_read(r.index("C")) | sr_write(sr.index("Z")),
sr_read(sr.index("WZ")) | mr_read(r.index("A")) | io_write | c_qw["reset_context"] | c_qw["reset_m_state"]
]
}
x=1
z = 2
q = 0
for p in range(3):
instructions[int(f"0b{x:02b}{((p<<1)+q):03b}{z:03b}", 2)] = {
"name": f"SBC HL, {rp[p]}",
"subins": [
f_to_flatch,
mr_read(r.index("L")) | c_qw["ACU_write_en"],
mr_read((p<<1)+1) | c_qw["TMP_write_en"],
alu_op(alu.index("SBC")) | mr_write(r.index("L")),
mr_read(r.index("H")) | c_qw["ACU_write_en"],
mr_read((p<<1)) | c_qw["TMP_write_en"],
alu_op(alu.index("SBC")) | mr_write(r.index("H")),
flatch_to_f | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=1
z = 2
p = rp.index("SP")
q = 0
instructions[int(f"0b{x:02b}{((p<<1)+q):03b}{z:03b}", 2)] = {
"name": f"SBC HL, SP",
"subins": [
f_to_flatch,
mr_read(r.index("H")) | c_qw["ACU_write_en"],
sr_read(sr.index("SPL")) | c_qw["TMP_write_en"],
alu_op(alu.index("SBC")) | mr_write(r.index("L")),
mr_read(r.index("H")) | c_qw["ACU_write_en"],
sr_read(sr.index("SPH")) | c_qw["TMP_write_en"],
alu_op(alu.index("SBC")) | mr_write(r.index("H")),
flatch_to_f | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=1
z = 2
q = 1
for p in range(3):
instructions[int(f"0b{x:02b}{((p<<1)+q):03b}{z:03b}", 2)] = {
"name": f"ADC HL, {rp[p]}",
"subins": [
f_to_flatch,
mr_read(r.index("L")) | c_qw["ACU_write_en"],
mr_read((p<<1)+1) | c_qw["TMP_write_en"],
alu_op(alu.index("ADC")) | mr_write(r.index("L")),
mr_read(r.index("H")) | c_qw["ACU_write_en"],
mr_read((p<<1)) | c_qw["TMP_write_en"],
alu_op(alu.index("ADC")) | mr_write(r.index("H")),
flatch_to_f | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=1
z = 2
p = rp.index("SP")
q = 1
instructions[int(f"0b{x:02b}{((p<<1)+q):03b}{z:03b}", 2)] = {
"name": f"ADC HL, SP",
"subins": [
f_to_flatch,
mr_read(r.index("H")) | c_qw["ACU_write_en"],
sr_read(sr.index("SPL")) | c_qw["TMP_write_en"],
alu_op(alu.index("ADC")) | mr_write(r.index("L")),
mr_read(r.index("H")) | c_qw["ACU_write_en"],
sr_read(sr.index("SPH")) | c_qw["TMP_write_en"],
alu_op(alu.index("ADC")) | mr_write(r.index("H")),
flatch_to_f | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=1
z = 3
q = 0
for p in range(3):
instructions[int(f"0b{x:02b}{((p<<1)+q):03b}{z:03b}", 2)] = {
"name": f"LD (nn), {rp[p]}",
"subins": [
sr_read(sr.index("PC")) | mem_read | sr_write(sr.index("Z")),
sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
sr_read(sr.index("PC")) | mem_read | sr_write(sr.index("W")),
sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
sr_read(sr.index("WZ")) | mr_read((p<<1)+1) | mem_write | c_qw["addr_inc_en"] | sr_write(sr.index("WZ")),
sr_read(sr.index("WZ")) | mr_read(p<<1) | mem_write | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=1
z = 3
p = rp.index("SP")
q = 0
instructions[int(f"0b{x:02b}{((p<<1)+q):03b}{z:03b}", 2)] = {
"name": f"LD (nn), SP",
"subins": [
sr_read(sr.index("PC")) | mem_read | sr_write(sr.index("Z")),
sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
sr_read(sr.index("PC")) | mem_read | sr_write(sr.index("W")),
sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
sr_read(sr.index("SPL")) | c_qw["TMP_write_en"],
sr_read(sr.index("WZ")) | tmp_to_db | mem_write | c_qw["addr_inc_en"] | sr_write(sr.index("WZ")),
sr_read(sr.index("SPH")) | c_qw["TMP_write_en"],
sr_read(sr.index("WZ")) | tmp_to_db | mem_write | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=1
z = 3
q = 1
for p in range(3):
instructions[int(f"0b{x:02b}{((p<<1)+q):03b}{z:03b}", 2)] = {
"name": f"LD {rp[p]}, (nn)",
"subins": [
sr_read(sr.index("PC")) | mem_read |sr_write(sr.index("Z")),
sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
sr_read(sr.index("PC")) | mem_read | sr_write(sr.index("W")),
sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
sr_read(sr.index("WZ")) | mem_read | mr_write((p<<1)+1),
sr_read(sr.index("WZ")) | c_qw["addr_inc_en"] | sr_write(sr.index("WZ")),
sr_read(sr.index("WZ")) | mem_read | mr_write(p<<1) | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=1
z = 3
p = rp.index("SP")
q = 1
instructions[int(f"0b{x:02b}{((p<<1)+q):03b}{z:03b}", 2)] = {
"name": f"LD SP, (nn)",
"subins": [
sr_read(sr.index("PC")) | mem_read |sr_write(sr.index("Z")),
sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
sr_read(sr.index("PC")) | mem_read | sr_write(sr.index("W")),
sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
sr_read(sr.index("WZ")) | mem_read | sr_write(sr.index("SPL")),
sr_read(sr.index("WZ")) | c_qw["addr_inc_en"] | sr_write(sr.index("WZ")),
sr_read(sr.index("WZ")) | mem_read | sr_write(sr.index("SPH")) | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=1
z=4
for y in range(8):
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"NEG",
"subins": [
clear_acu,
mr_read(r.index("A")) | c_qw["TMP_write_en"],
alu_op(alu.index("SUB")) | mr_write(r.index("A")),
flatch_to_f | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=1
z=5
for y in range(8):
if y == 1: continue
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"RETN",
"subins": [
c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=1
z=5
y=1
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"RETI",
"subins": [
c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=1
z=6
for y in range(8):
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"IM",
"subins": [
c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=1
z=5
y=1
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"RETI",
"subins": [
c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=1
z=5
for y in range(8):
if y in (4, 5): continue
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"NOP",
"subins": [
c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=1
z=5
y=4
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"RRD",
"subins": [
a_to_acu,
mr_read(r.index("(HL)")) | mem_read | c_qw["TMP_write_en"],
alu_op(rot.index("RRD"),alu_dev.index("SLU")) | mr_read(r.index("(HL)")) | mem_write,
alu_op(rot.index("RRD"),alu_dev.index("SLUA"),save_flags=False) | mr_write(r.index("A")),
flatch_to_f | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=1
z=5
y=5
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"RLD",
"subins": [
a_to_acu,
mr_read(r.index("(HL)")) | mem_read | c_qw["TMP_write_en"],
alu_op(rot.index("RLD"),alu_dev.index("SLU")) | mr_read(r.index("(HL)")) | mem_write,
alu_op(rot.index("RLD"),alu_dev.index("SLUA"),save_flags=False) | mr_write(r.index("A")),
flatch_to_f | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=2
y=4
z=0
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"LDI",
"subins": [
clear_acu,
mr_read(r.index("E")) | sr_write(sr.index("Z")),
mr_read(r.index("D")) | sr_write(sr.index("W")),
mr_read(r.index("(HL)")) | mem_read | c_qw["TMP_write_en"],
sr_read(sr.index("WZ")) | tmp_to_db | mem_write,
mr_read(r.index("E")) | c_qw["TMP_write_en"],
alu_op(inc.index("INC"),alu_dev.index("INC")) | mr_write(r.index("E")),
mr_read(r.index("D")) | c_qw["TMP_write_en"],
alu_op(alu.index("ADC")) | mr_write(r.index("D")),
mr_read(r.index("L")) | c_qw["TMP_write_en"],
alu_op(inc.index("INC"),alu_dev.index("INC")) | mr_write(r.index("L")),
mr_read(r.index("H")) | c_qw["TMP_write_en"],
alu_op(alu.index("ADC")) | mr_write(r.index("H")),
mr_read(r.index("C")) | c_qw["TMP_write_en"],
alu_op(inc.index("DEC"),alu_dev.index("INC")) | mr_write(r.index("C")),
clear_tmp,
mr_read(r.index("B")) | c_qw["ACU_write_en"],
alu_op(alu.index("SBC")) | mr_write(r.index("B")),
nop,
exec_if_cond(cc.index("Z")) | mr_read(r.index("C")) | c_qw["TMP_write_en"],
exec_if_cond(cc.index("Z")) | alu_op(0,alu_dev.index("INC")),
f_to_tmp,
alu_op(flags.index("P/V") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
alu_op(flags.index("N") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
alu_op(flags.index("H") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
exec_if_cond(cc.index("Z")) | alu_op(flags.index("P/V") | bit["SET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
tmp_to_db | c_qw["F_write_en"] | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=2
y=5
z=0
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"LDD",
"subins": [
clear_acu,
mr_read(r.index("E")) | sr_write(sr.index("Z")),
mr_read(r.index("D")) | sr_write(sr.index("W")),
mr_read(r.index("(HL)")) | mem_read | c_qw["TMP_write_en"],
sr_read(sr.index("WZ")) | tmp_to_db | mem_write,
mr_read(r.index("E")) | c_qw["TMP_write_en"],
alu_op(inc.index("DEC"),alu_dev.index("INC")) | mr_write(r.index("E")),
clear_tmp,
mr_read(r.index("D")) | c_qw["ACU_write_en"],
alu_op(alu.index("SBC")) | mr_write(r.index("D")),
mr_read(r.index("L")) | c_qw["TMP_write_en"],
alu_op(inc.index("DEC"),alu_dev.index("INC")) | mr_write(r.index("L")),
clear_tmp,
mr_read(r.index("H")) | c_qw["ACU_write_en"],
alu_op(alu.index("SBC")) | mr_write(r.index("H")),
mr_read(r.index("C")) | c_qw["TMP_write_en"],
alu_op(inc.index("DEC"),alu_dev.index("INC")) | mr_write(r.index("C")),
clear_tmp,
mr_read(r.index("B")) | c_qw["ACU_write_en"],
alu_op(alu.index("SBC")) | mr_write(r.index("B")),
nop,
exec_if_cond(cc.index("Z")) | mr_read(r.index("C")) | c_qw["TMP_write_en"],
exec_if_cond(cc.index("Z")) | alu_op(0,alu_dev.index("INC")),
f_to_tmp,
alu_op(flags.index("P/V") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
alu_op(flags.index("N") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
alu_op(flags.index("H") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
exec_if_cond(cc.index("Z")) | alu_op(flags.index("P/V") | bit["SET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
tmp_to_db | c_qw["F_write_en"] | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=2
y=6
z=0
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"LDIR",
"subins": [
clear_acu,
mr_read(r.index("E")) | sr_write(sr.index("Z")),
mr_read(r.index("D")) | sr_write(sr.index("W")),
mr_read(r.index("(HL)")) | mem_read | c_qw["TMP_write_en"],
sr_read(sr.index("WZ")) | tmp_to_db | mem_write,
mr_read(r.index("E")) | c_qw["TMP_write_en"],
alu_op(inc.index("INC"),alu_dev.index("INC")) | mr_write(r.index("E")),
mr_read(r.index("D")) | c_qw["TMP_write_en"],
alu_op(alu.index("ADC")) | mr_write(r.index("D")),
mr_read(r.index("L")) | c_qw["TMP_write_en"],
alu_op(inc.index("INC"),alu_dev.index("INC")) | mr_write(r.index("L")),
mr_read(r.index("H")) | c_qw["TMP_write_en"],
alu_op(alu.index("ADC")) | mr_write(r.index("H")),
mr_read(r.index("C")) | c_qw["TMP_write_en"],
alu_op(inc.index("DEC"),alu_dev.index("INC")) | mr_write(r.index("C")),
clear_tmp,
mr_read(r.index("B")) | c_qw["ACU_write_en"],
alu_op(alu.index("SBC")) | mr_write(r.index("B")),
nop,
exec_if_cond(cc.index("Z")) | mr_read(r.index("C")) | c_qw["TMP_write_en"],
exec_if_cond(cc.index("Z")) | alu_op(0,alu_dev.index("INC")),
nop,
exec_if_cond(cc.index("NZ")) | sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | c_qw["addr_dec"] | sr_write(sr.index("PC")),
exec_if_cond(cc.index("NZ")) | sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | c_qw["addr_dec"] | sr_write(sr.index("PC")),
f_to_tmp,
alu_op(flags.index("P/V") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
alu_op(flags.index("N") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
alu_op(flags.index("H") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
exec_if_cond(cc.index("Z")) | alu_op(flags.index("P/V") | bit["SET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
tmp_to_db | c_qw["F_write_en"],
c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=2
y=7
z=0
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"LDDR",
"subins": [
clear_acu,
mr_read(r.index("E")) | sr_write(sr.index("Z")),
mr_read(r.index("D")) | sr_write(sr.index("W")),
mr_read(r.index("(HL)")) | mem_read | c_qw["TMP_write_en"],
sr_read(sr.index("WZ")) | tmp_to_db | mem_write,
mr_read(r.index("E")) | c_qw["TMP_write_en"],
alu_op(inc.index("DEC"),alu_dev.index("INC")) | mr_write(r.index("E")),
clear_tmp,
mr_read(r.index("D")) | c_qw["ACU_write_en"],
alu_op(alu.index("SBC")) | mr_write(r.index("D")),
mr_read(r.index("L")) | c_qw["TMP_write_en"],
alu_op(inc.index("DEC"),alu_dev.index("INC")) | mr_write(r.index("L")),
clear_tmp,
mr_read(r.index("H")) | c_qw["ACU_write_en"],
alu_op(alu.index("SBC")) | mr_write(r.index("H")),
mr_read(r.index("C")) | c_qw["TMP_write_en"],
alu_op(inc.index("DEC"),alu_dev.index("INC")) | mr_write(r.index("C")),
clear_tmp,
mr_read(r.index("B")) | c_qw["ACU_write_en"],
alu_op(alu.index("SBC")) | mr_write(r.index("B")),
nop,
exec_if_cond(cc.index("Z")) | mr_read(r.index("C")) | c_qw["TMP_write_en"],
exec_if_cond(cc.index("Z")) | alu_op(0,alu_dev.index("INC")),
nop,
exec_if_cond(cc.index("NZ")) | sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | c_qw["addr_dec"] | sr_write(sr.index("PC")),
exec_if_cond(cc.index("NZ")) | sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | c_qw["addr_dec"] | sr_write(sr.index("PC")),
f_to_tmp,
alu_op(flags.index("P/V") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
alu_op(flags.index("N") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
alu_op(flags.index("H") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
exec_if_cond(cc.index("Z")) | alu_op(flags.index("P/V") | bit["SET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
tmp_to_db | c_qw["F_write_en"] | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=2
y=4
z=1
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"CPI",
"subins": [
a_to_acu,
mr_read(r.index("(HL)")) | mem_read | c_qw["TMP_write_en"],
alu_op(alu.index("SUB")),
flatch_to_f,
mr_read(r.index("L")) | c_qw["TMP_write_en"],
alu_op(inc.index("INC"),alu_dev.index("INC")) | mr_write(r.index("L")),
mr_read(r.index("H")) | c_qw["TMP_write_en"],
alu_op(alu.index("ADC")) | mr_write(r.index("H")),
mr_read(r.index("C")) | c_qw["TMP_write_en"],
alu_op(inc.index("DEC"),alu_dev.index("INC")) | mr_write(r.index("C")),
clear_tmp,
mr_read(r.index("B")) | c_qw["ACU_write_en"],
alu_op(alu.index("SBC")) | mr_write(r.index("B")),
f_to_tmp,
alu_op(flags.index("P/V") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
exec_if_cond(cc.index("Z")) | alu_op(flags.index("P/V") | bit["SET"],alu_dev.index("BMU"),False) | c_qw["F_write_en"] | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=2
y=5
z=1
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"CPD",
"subins": [
a_to_acu,
mr_read(r.index("(HL)")) | mem_read | c_qw["TMP_write_en"],
alu_op(alu.index("SUB")),
flatch_to_f,
mr_read(r.index("L")) | c_qw["TMP_write_en"],
alu_op(inc.index("DEC"),alu_dev.index("INC")) | mr_write(r.index("L")),
clear_tmp,
mr_read(r.index("H")) | c_qw["ACU_write_en"],
alu_op(alu.index("SBC")) | mr_write(r.index("H")),
mr_read(r.index("C")) | c_qw["TMP_write_en"],
alu_op(inc.index("DEC"),alu_dev.index("INC")) | mr_write(r.index("C")),
clear_tmp,
mr_read(r.index("B")) | c_qw["ACU_write_en"],
alu_op(alu.index("SBC")) | mr_write(r.index("B")),
f_to_tmp,
alu_op(flags.index("P/V") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
exec_if_cond(cc.index("Z")) | alu_op(flags.index("P/V") | bit["SET"],alu_dev.index("BMU"),False) | c_qw["F_write_en"] | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=2
y=6
z=1
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"CPIR",
"subins": [
a_to_acu,
mr_read(r.index("(HL)")) | mem_read | c_qw["TMP_write_en"],
alu_op(alu.index("SUB")),
flatch_to_f,
mr_read(r.index("L")) | c_qw["TMP_write_en"],
alu_op(inc.index("INC"),alu_dev.index("INC")) | mr_write(r.index("L")),
mr_read(r.index("H")) | c_qw["TMP_write_en"],
alu_op(alu.index("ADC")) | mr_write(r.index("H")),
mr_read(r.index("C")) | c_qw["TMP_write_en"],
alu_op(inc.index("DEC"),alu_dev.index("INC")) | mr_write(r.index("C")),
clear_tmp,
mr_read(r.index("B")) | c_qw["ACU_write_en"],
alu_op(alu.index("SBC")) | mr_write(r.index("B")),
f_to_tmp,
alu_op(flags.index("P/V") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
exec_if_cond(cc.index("Z")) | alu_op(flags.index("P/V") | bit["SET"],alu_dev.index("BMU"),False) | c_qw["F_write_en"],
f_to_flatch,
nop,
exec_if_cond(cc.index("PE")) | sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | c_qw["addr_dec"] | sr_write(sr.index("PC")),
exec_if_cond(cc.index("PE")) | sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | c_qw["addr_dec"] | sr_write(sr.index("PC")) | c_qw["reset_m_state"] | c_qw["reset_context"],
exec_if_cond(cc.index("NZ")) | sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | c_qw["addr_dec"] | sr_write(sr.index("PC")),
exec_if_cond(cc.index("NZ")) | sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | c_qw["addr_dec"] | sr_write(sr.index("PC")) | c_qw["reset_m_state"] | c_qw["reset_context"],
c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=2
y=7
z=1
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"CPDR",
"subins": [
clear_acu,
mr_read(r.index("(HL)")) | mem_read | c_qw["TMP_write_en"],
alu_op(alu.index("SUB")),
flatch_to_f,
mr_read(r.index("L")) | c_qw["TMP_write_en"],
alu_op(inc.index("DEC"),alu_dev.index("INC")) | mr_write(r.index("L")),
clear_tmp,
mr_read(r.index("H")) | c_qw["ACU_write_en"],
alu_op(alu.index("SBC")) | mr_write(r.index("H")),
mr_read(r.index("C")) | c_qw["TMP_write_en"],
alu_op(inc.index("DEC"),alu_dev.index("INC")) | mr_write(r.index("C")),
clear_tmp,
mr_read(r.index("B")) | c_qw["ACU_write_en"],
alu_op(alu.index("SBC")) | mr_write(r.index("B")),
f_to_tmp,
alu_op(flags.index("P/V") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
exec_if_cond(cc.index("Z")) | alu_op(flags.index("P/V") | bit["SET"],alu_dev.index("BMU"),False) | c_qw["F_write_en"],
f_to_flatch,
nop,
exec_if_cond(cc.index("PE")) | sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | c_qw["addr_dec"] | sr_write(sr.index("PC")),
exec_if_cond(cc.index("PE")) | sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | c_qw["addr_dec"] | sr_write(sr.index("PC")) | c_qw["reset_m_state"] | c_qw["reset_context"],
exec_if_cond(cc.index("NZ")) | sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | c_qw["addr_dec"] | sr_write(sr.index("PC")),
exec_if_cond(cc.index("NZ")) | sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | c_qw["addr_dec"] | sr_write(sr.index("PC")) | c_qw["reset_m_state"] | c_qw["reset_context"],
c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
x=2
y=4
z=2
instructions[int(f"0b{x:02b}{y:03b}{z:03b}", 2)] = {
"name": f"INI",
"subins": [
clear_acu,
mr_read(r.index("C")) | sr_write(sr.index("Z")),
sr_read(sr.index("WZ")) | io_read | c_qw["TMP_write_en"],
mr_read(r.index("(HL)")) | tmp_to_db | mem_write,
mr_read(r.index("L")) | c_qw["TMP_write_en"],
alu_op(inc.index("INC"),alu_dev.index("INC")) | mr_write(r.index("L")),
mr_read(r.index("H")) | c_qw["TMP_write_en"],
alu_op(alu.index("ADC")) | mr_write(r.index("H")),
c_qw["Flatch_read_en"] | c_qw["ACU_write_en"],
alu_op(flags.index("C") | bit["SET"],alu_dev.index("BMU")) | c_qw["TMP_write_en"],
alu_op(alu.index("AND")) | sr_write(sr.index("Z")), # Z = 0b0000000C
mr_read(r.index("B")) | c_qw["TMP_write_en"],
alu_op(inc.index("DEC"),alu_dev.index("INC")) | mr_write(r.index("B")),
f_to_tmp,
alu_op(flags.index("Z") | bit["RESET"],alu_dev.index("BMU"),save_flags=False) | c_qw["TMP_write_en"],
alu_op(flags.index("C") | bit["RESET"],alu_dev.index("BMU"),save_flags=False) | c_qw["TMP_write_en"],
sr_read(sr.index("Z")) | c_qw["ACU_write_en"],
alu_op(alu.index("OR"),0,save_flags=False) | c_qw["TMP_write_en"],
exec_if_cond(cc.index("Z")) | alu_op(flags.index("Z") | bit["SET"],alu_dev.index("BMU"),False) | c_qw["F_write_en"],
f_to_flatch | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}

590
quadrants/mq0.py Normal file
View File

@ -0,0 +1,590 @@
from z80shortcuts import *
instructions = [None] * 256
y = 0
z = 0
instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
"name": "NOP",
"subins": [
c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
y = 1
z = 0
instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
"name": "EX AF, AF'",
"subins": [
c_qw["AF_toggle"] | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
y = 2
z = 0
instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
"name": "DJNZ d",
"subins": [
sr_read(sr.index("PC")) | mem_read | c_qw["ACU_write_en"] | c_qw["TMP_write_en"] | sr_write(sr.index("Z")),
sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
#sign extend
alu_op(alu.index("ADD")),
alu_op(alu.index("SBC")) | sr_write(sr.index("W")),
sr_read(sr.index("PCL")) | c_qw["ACU_write_en"],
sr_read(sr.index("Z")) | c_qw["TMP_write_en"],
alu_op(alu.index("ADD")) | sr_write(sr.index("Z")),
sr_read(sr.index("PCH")) | c_qw["ACU_write_en"],
sr_read(sr.index("W")) | c_qw["TMP_write_en"],
alu_op(alu.index("ADC")) | sr_write(sr.index("W")),
clear_acu,
mr_read(r.index("B")) | c_qw["TMP_write_en"],
alu_op(inc.index("DEC"),alu_dev.index("INC")) | mr_write(r.index("B")),
exec_if_cond(cc_i["NZ"]) | c_qw["reset_m_state"] | c_qw["reset_context"],
sr_read(sr.index("WZ")) | sr_write(sr.index("PC")) | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
y = 3
z = 0
instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
"name": "JR d",
"subins": [
sr_read(sr.index("PC")) | mem_read | c_qw["ACU_write_en"] | c_qw["TMP_write_en"] | sr_write(sr.index("Z")),
sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
#sign extend
alu_op(alu.index("ADD")),
alu_op(alu.index("SBC")) | sr_write(sr.index("W")),
sr_read(sr.index("PCL")) | c_qw["ACU_write_en"],
sr_read(sr.index("Z")) | c_qw["TMP_write_en"],
alu_op(alu.index("ADD")) | sr_write(sr.index("Z")),
sr_read(sr.index("PCH")) | c_qw["ACU_write_en"],
sr_read(sr.index("W")) | c_qw["TMP_write_en"],
alu_op(alu.index("ADC")) | sr_write(sr.index("W")),
sr_read(sr.index("WZ")) | sr_write(sr.index("PC")) | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
z = 0
for y in [4, 5, 6, 7]:
instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
"name": f"JR {cc[y-4]}, d",
"subins": [
sr_read(sr.index("PC")) | mem_read | c_qw["ACU_write_en"] | c_qw["TMP_write_en"] | sr_write(sr.index("Z")),
sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
#early return
f_to_flatch,
exec_if_cond(cc_i[cc[(y-4)]]) | c_qw["reset_m_state"] | c_qw["reset_context"],
#sign extend
alu_op(alu.index("ADD")),
alu_op(alu.index("SBC")) | sr_write(sr.index("W")),
sr_read(sr.index("PCL")) | c_qw["ACU_write_en"],
sr_read(sr.index("Z")) | c_qw["TMP_write_en"], # unneeded
alu_op(alu.index("ADD")) | sr_write(sr.index("Z")),
sr_read(sr.index("PCH")) | c_qw["ACU_write_en"],
sr_read(sr.index("W")) | c_qw["TMP_write_en"],
alu_op(alu.index("ADC")) | sr_write(sr.index("W")),
sr_read(sr.index("WZ")) | sr_write(sr.index("PC")) | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
z = 1
for y in range(8):
p = y >> 1
q = y & 1
if q != 0: continue
if p == 3: continue
instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
"name": f"LD {rp[p]}, nn",
"subins": [
sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")) | mem_read | mr_write((p<<1)+1),
sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")) | mem_read | mr_write((p<<1)) | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
z = 1
y = 6
instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
"name": f"LD SP, nn",
"subins": [
sr_read(sr.index("PC")) | mem_read | sr_write(sr.index("SPL")),
sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
sr_read(sr.index("PC")) | mem_read | sr_write(sr.index("SPH")),
sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")) | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
z = 1
for y in range(8):
p = y >> 1
q = y & 1
if q == 0: continue
if p == 3: continue
instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
"name": f"ADD HL, {rp[p]}",
"subins": [
mr_read(r.index("L")) | c_qw["ACU_write_en"],
mr_read((p<<1)+1) | c_qw["TMP_write_en"],
alu_op(alu.index("ADD")) | mr_write(r.index("L")),
mr_read(r.index("H")) | c_qw["ACU_write_en"],
mr_read((p<<1)) | c_qw["TMP_write_en"],
alu_op(alu.index("ADC")) | mr_write(r.index("H")),
flatch_to_f | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
z = 1
p = rp.index("SP")
q = 1
instructions[int(f"0b00{((p<<1)+q):03b}{z:03b}", 2)] = {
"name": f"ADD HL, SP",
"subins": [
mr_read(r.index("L")) | c_qw["ACU_write_en"],
sr_read(sr.index("SPL")) | c_qw["TMP_write_en"],
alu_op(alu.index("ADD")) | mr_write(r.index("L")),
mr_read(r.index("H")) | c_qw["ACU_write_en"],
sr_read(sr.index("SPH")) | c_qw["TMP_write_en"],
alu_op(alu.index("ADC")) | mr_write(r.index("H")),
flatch_to_f | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
z = 2
q = 0
p = 0
instructions[int(f"0b00{((p<<1)+q):03b}{z:03b}", 2)] = {
"name": f"LD (BC), A",
"subins": [
mr_read(r.index("B")) | sr_write(sr.index("W")),
mr_read(r.index("C")) | sr_write(sr.index("Z")),
sr_read(sr.index("WZ")) | mr_read(r.index("A")) | mem_write | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
z = 2
q = 0
p = 1
instructions[int(f"0b00{((p<<1)+q):03b}{z:03b}", 2)] = {
"name": f"LD (DE), A",
"subins": [
mr_read(r.index("D")) | sr_write(sr.index("W")),
mr_read(r.index("E")) | sr_write(sr.index("Z")),
sr_read(sr.index("WZ")) | mr_read(r.index("A")) | mem_write | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
z = 2
q = 0
p = 2
instructions[int(f"0b00{((p<<1)+q):03b}{z:03b}", 2)] = {
"name": f"LD (nn), HL",
"subins": [
sr_read(sr.index("PC")) | mem_read | sr_write(sr.index("Z")),
sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
sr_read(sr.index("PC")) | mem_read | sr_write(sr.index("W")),
sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
sr_read(sr.index("WZ")) | mr_read(r.index("L")) | mem_write | c_qw["addr_inc_en"] | sr_write(sr.index("WZ")),
sr_read(sr.index("WZ")) | mr_read(r.index("H")) | mem_write | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
z = 2
q = 0
p = 3
instructions[int(f"0b00{((p<<1)+q):03b}{z:03b}", 2)] = {
"name": f"LD (nn), A",
"subins": [
sr_read(sr.index("PC")) | mem_read | sr_write(sr.index("Z")),
sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
sr_read(sr.index("PC")) | mem_read | sr_write(sr.index("W")),
sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
sr_read(sr.index("WZ")) | mr_read(r.index("A")) | mem_write | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
z = 2
q = 1
p = 0
instructions[int(f"0b00{((p<<1)+q):03b}{z:03b}", 2)] = {
"name": f"LD A, (BC)",
"subins": [
mr_read(r.index("B")) | sr_write(sr.index("W")),
mr_read(r.index("C")) | sr_write(sr.index("Z")),
sr_read(sr.index("WZ")) | mem_read | mr_write(r.index("A")) | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
z = 2
q = 1
p = 1
instructions[int(f"0b00{((p<<1)+q):03b}{z:03b}", 2)] = {
"name": f"LD A, (DE)",
"subins": [
mr_read(r.index("D")) | sr_write(sr.index("W")),
mr_read(r.index("E")) | sr_write(sr.index("Z")),
sr_read(sr.index("WZ")) | mem_read | mr_write(r.index("A")) | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
z = 2
q = 1
p = 2
instructions[int(f"0b00{((p<<1)+q):03b}{z:03b}", 2)] = {
"name": f"LD HL, (nn)",
"subins": [
sr_read(sr.index("PC")) | mem_read |sr_write(sr.index("Z")),
sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
sr_read(sr.index("PC")) | mem_read | sr_write(sr.index("W")),
sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
sr_read(sr.index("WZ")) | mem_read | mr_write(r.index("L")),
sr_read(sr.index("WZ")) | c_qw["addr_inc_en"] | sr_write(sr.index("WZ")),
sr_read(sr.index("WZ")) | mem_read | mr_write(r.index("H")) | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
z = 2
q = 1
p = 3
instructions[int(f"0b00{((p<<1)+q):03b}{z:03b}", 2)] = {
"name": f"LD A, (nn)",
"subins": [
sr_read(sr.index("PC")) | mem_read | sr_write(sr.index("Z")),
sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
sr_read(sr.index("PC")) | mem_read | sr_write(sr.index("W")),
sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
sr_read(sr.index("WZ")) | mem_read | mr_write(r.index("A")) | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
z = 3
q = 0
for p in range(3):
instructions[int(f"0b00{((p<<1)+q):03b}{z:03b}", 2)] = {
"name": f"INC {rp[p]}",
"subins": [
clear_acu,
mr_read((p<<1)+1) | c_qw["TMP_write_en"],
alu_op(inc.index("INC"),alu_dev.index("INC")) | mr_write((p<<1)+1),
mr_read((p<<1)) | c_qw["TMP_write_en"],
alu_op(alu.index("ADC")) | mr_write((p<<1)) | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
z = 3
q = 0
p = rp.index("SP")
instructions[int(f"0b00{((p<<1)+q):03b}{z:03b}", 2)] = {
"name": f"INC SP",
"subins": [
clear_acu,
sr_read(sr.index("SPL")) | c_qw["TMP_write_en"],
alu_op(inc.index("INC"),alu_dev.index("INC")) | sr_write(sr.index("SPL")),
sr_read(sr.index("SPH")) | c_qw["TMP_write_en"],
alu_op(alu.index("ADC")) | sr_write(sr.index("SPH")) | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
z = 3
q = 1
for p in range(2):
instructions[int(f"0b00{((p<<1)+q):03b}{z:03b}", 2)] = {
"name": f"DEC {rp[p]}",
"subins": [
clear_acu,
mr_read((p<<1)+1) | c_qw["TMP_write_en"],
alu_op(inc.index("DEC"),alu_dev.index("INC")) | mr_write((p<<1)+1),
clear_tmp,
mr_read((p<<1)) | c_qw["ACU_write_en"],
alu_op(alu.index("SBC")) | mr_write((p<<1)) | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
z = 3
q = 1
p = rp.index("SP")
instructions[int(f"0b00{((p<<1)+q):03b}{z:03b}", 2)] = {
"name": f"DEC SP",
"subins": [
clear_acu,
sr_read(sr.index("SPL")) | c_qw["TMP_write_en"],
alu_op(inc.index("DEC"),alu_dev.index("INC")) | sr_write(sr.index("SPL")),
clear_tmp,
sr_read(sr.index("SPH")) | c_qw["ACU_write_en"],
alu_op(alu.index("SBC")) | sr_write(sr.index("SPH")) | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
z = 4
for y in range(8):
if y == r.index("(HL)"): continue
instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
"name": f"INC {r[y]}",
"subins": [
clear_acu,
mr_read(y) | c_qw["TMP_write_en"],
alu_op(inc.index("INC"),alu_dev.index("INC")) | mr_write(y),
flatch_to_f | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
z = 4
y = r.index("(HL)")
instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
"name": f"INC (HL)",
"subins": [
exec_if_context | sr_read(sr.index("PC")) | mem_read | c_qw["ACU_write_en"] | c_qw["TMP_write_en"] | sr_write(sr.index("Z")),
exec_if_context | sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
#sign extend
exec_if_context | alu_op(alu.index("ADD")),
exec_if_context | alu_op(alu.index("SBC")) | sr_write(sr.index("W")),
exec_if_context | mr_read(r.index("L")) | c_qw["ACU_write_en"],
exec_if_context | sr_read(sr.index("Z")) | c_qw["TMP_write_en"],
exec_if_context | alu_op(alu.index("ADD")) | sr_write(sr.index("Z")),
exec_if_context | mr_read(r.index("H")) | c_qw["ACU_write_en"],
exec_if_context | sr_read(sr.index("W")) | c_qw["TMP_write_en"],
exec_if_context | alu_op(alu.index("ADC")) | sr_write(sr.index("W")),
clear_acu,
mr_read(r.index("(HL)")) | mem_read | c_qw["TMP_write_en"],
alu_op(inc.index("INC"),alu_dev.index("INC")) | mr_read(y) | mem_write,
flatch_to_f | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
z = 5
for y in range(8):
if y == r.index("(HL)"): continue
instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
"name": f"DEC {r[y]}",
"subins": [
clear_acu,
mr_read(y) | c_qw["TMP_write_en"],
alu_op(inc.index("DEC"),alu_dev.index("INC")) | mr_write(y),
flatch_to_f | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
z = 5
y = r.index("(HL)")
instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
"name": f"DEC (HL)",
"subins": [
exec_if_context | sr_read(sr.index("PC")) | mem_read | c_qw["ACU_write_en"] | c_qw["TMP_write_en"] | sr_write(sr.index("Z")),
exec_if_context | sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
#sign extend
exec_if_context | alu_op(alu.index("ADD")),
exec_if_context | alu_op(alu.index("SBC")) | sr_write(sr.index("W")),
exec_if_context | mr_read(r.index("L")) | c_qw["ACU_write_en"],
exec_if_context | sr_read(sr.index("Z")) | c_qw["TMP_write_en"],
exec_if_context | alu_op(alu.index("ADD")) | sr_write(sr.index("Z")),
exec_if_context | mr_read(r.index("H")) | c_qw["ACU_write_en"],
exec_if_context | sr_read(sr.index("W")) | c_qw["TMP_write_en"],
exec_if_context | alu_op(alu.index("ADC")) | sr_write(sr.index("W")),
clear_acu,
mr_read(r.index("(HL)")) | mem_read | c_qw["TMP_write_en"],
alu_op(inc.index("DEC"),alu_dev.index("INC")) | mr_read(y) | mem_write,
flatch_to_f | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
z = 6
for y in range(8):
if y == r.index("(HL)"): continue
instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
"name": f"LD {r[y]}, n",
"subins": [
sr_read(sr.index("PC")) | mem_read | mr_write(y) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")) | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
z = 6
y = r.index("(HL)")
instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
"name": f"LD (HL), n",
"subins": [
exec_if_context | sr_read(sr.index("PC")) | mem_read | c_qw["ACU_write_en"] | c_qw["TMP_write_en"] | sr_write(sr.index("Z")),
exec_if_context | sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
#sign extend
exec_if_context | alu_op(alu.index("ADD")),
exec_if_context | alu_op(alu.index("SBC")) | sr_write(sr.index("W")),
exec_if_context | mr_read(r.index("L")) | c_qw["ACU_write_en"],
exec_if_context | sr_read(sr.index("Z")) | c_qw["TMP_write_en"],
exec_if_context | alu_op(alu.index("ADD")) | sr_write(sr.index("Z")),
exec_if_context | mr_read(r.index("H")) | c_qw["ACU_write_en"],
exec_if_context | sr_read(sr.index("W")) | c_qw["TMP_write_en"],
exec_if_context | alu_op(alu.index("ADC")) | sr_write(sr.index("W")),
sr_read(sr.index("PC")) | mem_read | c_qw["TMP_write_en"] | c_qw["addr_inc_en"] | sr_write(sr.index("PC")), # super hacky to preserve WZ for (IX+d)
mr_read(r.index("(HL)")) | tmp_to_db | mem_write | c_qw["reset_m_state"] | c_qw["reset_context"] # passthru tmp => DB
]
}
z = 7
y = 0
instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
"name": "RLCA",
"subins": [
f_to_flatch,
mr_read(r.index("A")) | c_qw["TMP_write_en"],
alu_op(rot.index("RLC"),alu_dev.index("SLU")) | mr_write(r.index("A")),
c_qw["Flatch_read_en"] | c_qw["ACU_write_en"],
clear_tmp,
alu_op(flags.index("C") | bit["SET"],alu_dev.index("BMU")) | c_qw["TMP_write_en"],
alu_op(alu.index("AND")) | sr_write(sr.index("Z")),
internal_byte_to_db(internal_byte.index("FF")) | c_qw["TMP_write_en"],
alu_op(flags.index("C") | bit["RESET"],alu_dev.index("BMU")) | c_qw["TMP_write_en"],
alu_op(flags.index("H") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
alu_op(flags.index("N") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"], #W = 0b11101100
c_qw["F_read_en"] | c_qw["ACU_write_en"],
alu_op(alu.index("AND")) | c_qw["ACU_write_en"],
sr_write(sr.index("Z")) | c_qw["TMP_write_en"],
alu_op(alu.index("OR")) | c_qw["F_write_en"]| c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
z = 7
y = 1
instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
"name": "RRCA",
"subins": [
f_to_flatch,
mr_read(r.index("A")) | c_qw["TMP_write_en"],
alu_op(rot.index("RRC"),alu_dev.index("SLU")) | mr_write(r.index("A")),
c_qw["Flatch_read_en"] | c_qw["ACU_write_en"],
clear_tmp,
alu_op(flags.index("C") | bit["SET"],alu_dev.index("BMU")) | c_qw["TMP_write_en"],
alu_op(alu.index("AND")) | sr_write(sr.index("Z")), # Z = 0b0000000C
internal_byte_to_db(internal_byte.index("FF")) | c_qw["TMP_write_en"],
alu_op(flags.index("C") | bit["RESET"],alu_dev.index("BMU")) | c_qw["TMP_write_en"],
alu_op(flags.index("H") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
alu_op(flags.index("N") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"], #W = 0b11101100
c_qw["F_read_en"] | c_qw["ACU_write_en"],
alu_op(alu.index("AND")) | c_qw["ACU_write_en"],
sr_write(sr.index("Z")) | c_qw["TMP_write_en"],
alu_op(alu.index("OR")) | c_qw["F_write_en"]| c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
z = 7
y = 2
instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
"name": "RLA",
"subins": [
mr_read(r.index("A")) | c_qw["TMP_write_en"],
alu_op(rot.index("RL"),alu_dev.index("SLU"))| mr_write(r.index("A")),
c_qw["Flatch_read_en"] | c_qw["ACU_write_en"],
clear_tmp,
alu_op(flags.index("C") | bit["SET"],alu_dev.index("BMU")) | c_qw["TMP_write_en"],
alu_op(alu.index("AND")) | sr_write(sr.index("Z")), # Z = 0b0000000C
internal_byte_to_db(internal_byte.index("FF")) | c_qw["TMP_write_en"],
alu_op(flags.index("C") | bit["RESET"],alu_dev.index("BMU")) | c_qw["TMP_write_en"],
alu_op(flags.index("H") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
alu_op(flags.index("N") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"], #W = 0b11101100
c_qw["F_read_en"] | c_qw["ACU_write_en"],
alu_op(alu.index("AND")) | c_qw["ACU_write_en"],
sr_write(sr.index("Z")) | c_qw["TMP_write_en"],
alu_op(alu.index("OR")) | c_qw["F_write_en"]| c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
z = 7
y = 3
instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
"name": "RRA",
"subins": [
mr_read(r.index("A")) | c_qw["TMP_write_en"],
alu_op(rot.index("RR"),alu_dev.index("SLU"))| mr_write(r.index("A")),
c_qw["Flatch_read_en"] | c_qw["ACU_write_en"],
clear_tmp,
alu_op(flags.index("C") | bit["SET"],alu_dev.index("BMU")) | c_qw["TMP_write_en"],
alu_op(alu.index("AND")) | sr_write(sr.index("Z")), # Z = 0b0000000C
internal_byte_to_db(internal_byte.index("FF")) | c_qw["TMP_write_en"],
alu_op(flags.index("C") | bit["RESET"],alu_dev.index("BMU")) | c_qw["TMP_write_en"],
alu_op(flags.index("H") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
alu_op(flags.index("N") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"], #W = 0b11101100
c_qw["F_read_en"] | c_qw["ACU_write_en"],
alu_op(alu.index("AND")) | c_qw["ACU_write_en"],
sr_write(sr.index("Z")) | c_qw["TMP_write_en"],
alu_op(alu.index("OR")) | c_qw["F_write_en"] | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
z = 7
y = 4
instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
"name": "DAA",
"subins": [
f_to_flatch,
a_to_acu,
alu_op(0,alu_dev.index("DAA")) | mr_write(r.index("A")),
flatch_to_f | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
z = 7
y = 5
instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
"name": "CPL",
"subins": [
a_to_acu,
alu_op(alu.index("NOT"),save_flags=False) | mr_write(r.index("A")),
f_to_tmp,
alu_op(flags.index("H") | bit["SET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
alu_op(flags.index("N") | bit["SET"],alu_dev.index("BMU"),False) | c_qw["F_write_en"] | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
z = 7
y = 6
instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
"name": "SCF",
"subins": [
f_to_tmp,
alu_op(flags.index("C") | bit["SET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
alu_op(flags.index("H") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
alu_op(flags.index("N") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["F_write_en"] | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
z = 7
y = 7
instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
"name": "CCF",
"subins": [
f_to_acu,
clear_tmp,
alu_op(flags.index("C") | bit["SET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
alu_op(flags.index("H") | bit["SET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
alu_op(alu.index("XOR"),save_flags=False) | c_qw["TMP_write_en"],
alu_op(flags.index("N") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["F_write_en"] | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}

75
quadrants/mq1.py Normal file
View File

@ -0,0 +1,75 @@
from z80shortcuts import *
instructions = [None] * 256
for y in range(8):
for z in range(8):
if y == r.index("(HL)") or z == r.index("(HL)"):
continue
instructions[int(f"0b01{y:03b}{z:03b}", 2)] = {
"name": f"LD {r[y]}, {r[z]}",
"subins": [
mr_read(z) | mr_write(y) | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
y = 6
for z in range(8):
instructions[int(f"0b01{y:03b}{z:03b}", 2)] = {
"name": f"LD (HL), {r[z]}",
"subins": [
exec_if_context | sr_read(sr.index("PC")) | mem_read | c_qw["ACU_write_en"] | c_qw["TMP_write_en"] | sr_write(sr.index("Z")),
exec_if_context | sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
#sign extend
exec_if_context | alu_op(alu.index("ADD")),
exec_if_context | alu_op(alu.index("SBC")) | sr_write(sr.index("W")),
exec_if_context | mr_read(r.index("L")) | c_qw["ACU_write_en"],
exec_if_context | sr_read(sr.index("Z")) | c_qw["TMP_write_en"],
exec_if_context | alu_op(alu.index("ADD")) | sr_write(sr.index("Z")),
exec_if_context | mr_read(r.index("H")) | c_qw["ACU_write_en"],
exec_if_context | sr_read(sr.index("W")) | c_qw["TMP_write_en"],
exec_if_context | alu_op(alu.index("ADC")) | sr_write(sr.index("W")),
mr_read(r.index("(HL)")) | sr_write(sr.index("WZ")),
c_qw["reset_context"],
mr_read(z) | c_qw["TMP_write_en"],
sr_read(sr.index("WZ")) | tmp_to_db | mem_write | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
z = 6
for y in range(8):
instructions[int(f"0b01{y:03b}{z:03b}", 2)] = {
"name": f"LD {r[y]}, (HL)",
"subins": [
exec_if_context | sr_read(sr.index("PC")) | mem_read | c_qw["ACU_write_en"] | c_qw["TMP_write_en"] | sr_write(sr.index("Z")),
exec_if_context | sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
#sign extend
exec_if_context | alu_op(alu.index("ADD")),
exec_if_context | alu_op(alu.index("SBC")) | sr_write(sr.index("W")),
exec_if_context | mr_read(r.index("L")) | c_qw["ACU_write_en"],
exec_if_context | sr_read(sr.index("Z")) | c_qw["TMP_write_en"],
exec_if_context | alu_op(alu.index("ADD")) | sr_write(sr.index("Z")),
exec_if_context | mr_read(r.index("H")) | c_qw["ACU_write_en"],
exec_if_context | sr_read(sr.index("W")) | c_qw["TMP_write_en"],
exec_if_context | alu_op(alu.index("ADC")) | sr_write(sr.index("W")),
mr_read(r.index("(HL)")) | mem_read | c_qw["TMP_write_en"],
c_qw["reset_context"],
tmp_to_db | mr_write(y) | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
y = 6
z = 6
instructions[int(f"0b01{y:03b}{z:03b}", 2)] = {
"name": "HALT",
"subins": [
c_qw["HALT+"]
]
}

86
quadrants/mq2.py Normal file
View File

@ -0,0 +1,86 @@
from z80shortcuts import *
instructions = [None] * 256
for y in range(8):
for z in range(8):
if z == r.index("(HL)"): continue
if y == 7: continue
instructions[int(f"0b10{y:03b}{z:03b}", 2)] = {
"name": f"{alu[y]} {r[z]}",
"subins": [
f_to_flatch,
a_to_acu,
mr_read(z) | c_qw["TMP_write_en"],
alu_op(y,use_overflow=(y not in (4,5,6))) | mr_write(r.index("A")),
flatch_to_f | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
z=6
for y in range(8):
if y == 7: continue
instructions[int(f"0b10{y:03b}{z:03b}", 2)] = {
"name": f"{alu[y]} (HL)",
"subins": [
exec_if_context | sr_read(sr.index("PC")) | mem_read | c_qw["ACU_write_en"] | c_qw["TMP_write_en"] | sr_write(sr.index("Z")),
exec_if_context | sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
#sign extend
exec_if_context | alu_op(alu.index("ADD")),
exec_if_context | alu_op(alu.index("SBC")) | sr_write(sr.index("W")),
exec_if_context | mr_read(r.index("L")) | c_qw["ACU_write_en"],
exec_if_context | sr_read(sr.index("Z")) | c_qw["TMP_write_en"],
exec_if_context | alu_op(alu.index("ADD")) | sr_write(sr.index("Z")),
exec_if_context | mr_read(r.index("H")) | c_qw["ACU_write_en"],
exec_if_context | sr_read(sr.index("W")) | c_qw["TMP_write_en"],
exec_if_context | alu_op(alu.index("ADC")) | sr_write(sr.index("W")),
f_to_flatch,
a_to_acu,
mr_read(r.index("(HL)")) | mem_read | c_qw["TMP_write_en"],
alu_op(y,use_overflow=(y not in (4,5,6))) | mr_write(r.index('A')),
flatch_to_f | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
y = 7
for z in range(8):
if z == r.index("(HL)"): continue
instructions[int(f"0b10{y:03b}{z:03b}", 2)] = {
"name": f"CP {r[z]}",
"subins": [
f_to_flatch,
a_to_acu,
mr_read(z) | c_qw["TMP_write_en"],
alu_op(alu.index("SUB")),
flatch_to_f | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
y = 7
z = r.index("(HL)")
instructions[int(f"0b10{y:03b}{z:03b}", 2)] = {
"name": f"CP (HL)",
"subins": [
exec_if_context | sr_read(sr.index("PC")) | mem_read | c_qw["ACU_write_en"] | c_qw["TMP_write_en"] | sr_write(sr.index("Z")),
exec_if_context | sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
#sign extend
exec_if_context | alu_op(alu.index("ADD")),
exec_if_context | alu_op(alu.index("SBC")) | sr_write(sr.index("W")),
exec_if_context | mr_read(r.index("L")) | c_qw["ACU_write_en"],
exec_if_context | sr_read(sr.index("Z")) | c_qw["TMP_write_en"],
exec_if_context | alu_op(alu.index("ADD")) | sr_write(sr.index("Z")),
exec_if_context | mr_read(r.index("H")) | c_qw["ACU_write_en"],
exec_if_context | sr_read(sr.index("W")) | c_qw["TMP_write_en"],
exec_if_context | alu_op(alu.index("ADC")) | sr_write(sr.index("W")),
f_to_flatch,
a_to_acu,
mr_read(r.index("(HL)")) | mem_read | c_qw["TMP_write_en"],
alu_op(alu.index("SUB")),
flatch_to_f | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}

363
quadrants/mq3.py Normal file
View File

@ -0,0 +1,363 @@
from z80shortcuts import *
instructions = [None] * 256
z = 0
for y in range(8):
instructions[int(f"0b11{y:03b}{z:03b}", 2)] = {
"name": f"RET {cc[y]}",
"subins": [
exec_if_cond(cc_i[cc[y]]) | c_qw["reset_m_state"] | c_qw["reset_context"],
sr_read(sr.index("SP")) | mem_read | sr_write(sr.index("PCL")),
sr_read(sr.index("SP")) | c_qw["addr_inc_en"] | sr_write(sr.index("SP")),
sr_read(sr.index("SP")) | mem_read | sr_write(sr.index("PCH")),
sr_read(sr.index("SP")) | c_qw["addr_inc_en"] | sr_write(sr.index("SP")) | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
z = 1
q = 0
for p in range(3):
instructions[int(f"0b11{((p<<1)+q):03b}{z:03b}", 2)] = {
"name": f"POP {rp2[p]}",
"subins": [
sr_read(sr.index("SP")) | c_qw["addr_inc_en"] | sr_write(sr.index("SP")) | mem_read | mr_write((p*2)+1),
sr_read(sr.index("SP")) | c_qw["addr_inc_en"] | sr_write(sr.index("SP")) | mem_read | mr_write(p*2) | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
z = 1
q = 0
p = 3
instructions[int(f"0b11{((p<<1)+q):03b}{z:03b}", 2)] = {
"name": "POP AF",
"subins": [
sr_read(sr.index("SP")) | c_qw["addr_inc_en"] | sr_write(sr.index("SP")) | mem_read | c_qw["F_write_en"],
sr_read(sr.index("SP")) | c_qw["addr_inc_en"] | sr_write(sr.index("SP")) | mem_read | mr_write(r.index("A")) | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
z = 1
q = 1
p = 0
instructions[int(f"0b11{((p<<1)+q):03b}{z:03b}", 2)] = {
"name": "RET",
"subins": [
sr_read(sr.index("SP")) | mem_read | sr_write(sr.index("PCL")),
sr_read(sr.index("SP")) | c_qw["addr_inc_en"] | sr_write(sr.index("SP")),
sr_read(sr.index("SP")) | mem_read | sr_write(sr.index("PCH")),
sr_read(sr.index("SP")) | c_qw["addr_inc_en"] | sr_write(sr.index("SP")) | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
z = 1
q = 1
p = 1
instructions[int(f"0b11{((p<<1)+q):03b}{z:03b}", 2)] = {
"name": "EXX",
"subins": [
c_qw["shadow_reg_tgl"] | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
z = 1
q = 1
p = 2
instructions[int(f"0b11{((p<<1)+q):03b}{z:03b}", 2)] = {
"name": "JP (HL)", # actually jp to the address in hl
"subins": [
exec_if_context | sr_read(sr.index("PC")) | mem_read | c_qw["ACU_write_en"] | c_qw["TMP_write_en"] | sr_write(sr.index("Z")),
exec_if_context | sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
#sign extend
exec_if_context | alu_op(alu.index("ADD")),
exec_if_context | alu_op(alu.index("SBC")) | sr_write(sr.index("W")),
exec_if_context | mr_read(r.index("L")) | c_qw["ACU_write_en"],
exec_if_context | sr_read(sr.index("Z")) | c_qw["TMP_write_en"],
exec_if_context | alu_op(alu.index("ADD")) | sr_write(sr.index("Z")),
exec_if_context | mr_read(r.index("H")) | c_qw["ACU_write_en"],
exec_if_context | sr_read(sr.index("W")) | c_qw["TMP_write_en"],
exec_if_context | alu_op(alu.index("ADC")) | sr_write(sr.index("W")),
mr_read(r.index("(HL)")) | sr_write(sr.index("PC")) | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
z = 1
q = 1
p = 3
instructions[int(f"0b11{((p<<1)+q):03b}{z:03b}", 2)] = {
"name": "LD SP, HL",
"subins": [
mr_read(r.index("L")) | sr_write(sr.index("SPL")),
mr_read(r.index("H")) | sr_write(sr.index("SPH")) | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
z = 2
for y in range(8):
instructions[int(f"0b11{y:03b}{z:03b}", 2)] = {
"name": f"JP {cc[y]}, nn",
"subins": [
sr_read(sr.index("PC")) | mem_read | sr_write(sr.index("Z")),
sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
sr_read(sr.index("PC")) | mem_read | sr_write(sr.index("W")),
sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
#early return
f_to_flatch,
exec_if_cond(cc_i[cc[(y)]]) | c_qw["reset_m_state"] | c_qw["reset_context"],
sr_read(sr.index("WZ")) | sr_write(sr.index("PC")) | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
z = 3
y = 0
instructions[int(f"0b11{y:03b}{z:03b}", 2)] = {
"name": f"JP nn",
"subins": [
sr_read(sr.index("PC")) | mem_read | sr_write(sr.index("Z")),
sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
sr_read(sr.index("PC")) | mem_read | sr_write(sr.index("W")),
sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
sr_read(sr.index("WZ")) | sr_write(sr.index("PC")) | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
z = 3
y = 1
instructions[int(f"0b11{y:03b}{z:03b}", 2)] = {
"name": f"CB",
"subins": [
c_qw["CB_prefix_set"] | c_qw["reset_m_state"]
]
}
z = 3
y = 2
instructions[int(f"0b11{y:03b}{z:03b}", 2)] = {
"name": f"OUT (n), A",
"subins": [
sr_write(sr.index("W")), # clear W reg (unneeded for super optimization)
sr_read(sr.index("PC")) | mem_read | sr_write(sr.index("Z")),
sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
sr_read(sr.index("WZ")) | mr_read(r.index("A")) | io_write,
c_qw["reset_context"] | c_qw["reset_m_state"]
]
}
z = 3
y = 3
instructions[int(f"0b11{y:03b}{z:03b}", 2)] = {
"name": f"IN A, (n)",
"subins": [
sr_write(sr.index("W")), # clear W reg (unneeded for super optimization)
sr_read(sr.index("PC")) | mem_read | sr_write(sr.index("Z")),
sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
sr_read(sr.index("WZ")) | io_read | mr_write(r.index("A")),
c_qw["reset_context"] | c_qw["reset_m_state"]
]
}
z = 3
y = 4
instructions[int(f"0b11{y:03b}{z:03b}", 2)] = {
"name": f"EX (SP), HL",
"subins": [
sr_read(sr.index("SP")) | mem_read | sr_write(sr.index("Z")),
sr_read(sr.index("SP")) | c_qw["addr_inc_en"] | sr_write(sr.index("SP")),
sr_read(sr.index("SP")) | mem_read | sr_write(sr.index("W")),
sr_read(sr.index("SP")) | c_qw["addr_inc_en"] | c_qw["addr_dec"] | sr_write(sr.index("SP")),
sr_read(sr.index("SP")) | mr_read(r.index("L")) | mem_write | c_qw["addr_inc_en"] | sr_write(sr.index("SP")),
sr_read(sr.index("SP")) | mr_read(r.index("H")) | mem_write | c_qw["addr_inc_en"] | c_qw["addr_dec"] | sr_write(sr.index("SP")),
sr_read(sr.index("Z")) | mr_write(r.index("L")),
sr_read(sr.index("W")) | mr_write(r.index("H")) | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
z = 3
y = 5
instructions[int(f"0b11{y:03b}{z:03b}", 2)] = {
"name": f"EX DE, HL",
"subins": [
mr_read(r.index("E")) | mem_read | sr_write(sr.index("Z")),
mr_read(r.index("D")) | mem_read | sr_write(sr.index("W")),
mr_read(r.index("L")) | mem_read | mr_write(r.index("E")),
mr_read(r.index("H")) | mem_read | mr_write(r.index("D")),
sr_read(sr.index("Z")) | mr_write(r.index("L")),
sr_read(sr.index("W")) | mr_write(r.index("H")) | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
z = 3
y = 6
instructions[int(f"0b11{y:03b}{z:03b}", 2)] = {
"name": f"DI",
"subins": [
c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
z = 3
y = 7
instructions[int(f"0b11{y:03b}{z:03b}", 2)] = {
"name": f"EI",
"subins": [
c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
z = 4
for y in range(8):
instructions[int(f"0b11{y:03b}{z:03b}", 2)] = {
"name": f"CALL {cc[y]}, nn",
"subins": [
sr_read(sr.index("PC")) | mem_read | sr_write(sr.index("Z")),
sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
sr_read(sr.index("PC")) | mem_read | sr_write(sr.index("W")),
sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
#early return
f_to_flatch,
exec_if_cond(cc_i[cc[(y)]]) | c_qw["reset_m_state"] | c_qw["reset_context"],
sr_read(sr.index("SP")) | c_qw["addr_inc_en"] | c_qw["addr_dec"] | sr_write(sr.index("SP")),
sr_read(sr.index("PCH")) | c_qw["TMP_write_en"],
sr_read(sr.index("SP")) | tmp_to_db | mem_write,
sr_read(sr.index("SP")) | c_qw["addr_inc_en"] | c_qw["addr_dec"] | sr_write(sr.index("SP")),
sr_read(sr.index("PCL")) | c_qw["TMP_write_en"],
sr_read(sr.index("SP")) | tmp_to_db | mem_write,
sr_read(sr.index("WZ")) | sr_write(sr.index("PC")) | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
z = 5
q = 0
for p in range(3):
instructions[int(f"0b11{((p<<1)+q):03b}{z:03b}", 2)] = {
"name": f"PUSH {rp2[p]}",
"subins": [
sr_read(sr.index("SP")) | c_qw["addr_inc_en"] | c_qw["addr_dec"] | sr_write(sr.index("SP")),
sr_read(sr.index("SP")) | mem_write | mr_read(p*2),
sr_read(sr.index("SP")) | c_qw["addr_inc_en"] | c_qw["addr_dec"] | sr_write(sr.index("SP")),
sr_read(sr.index("SP")) | mem_write | mr_read((p*2)+1) | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
z = 5
q = 0
p = 3
instructions[int(f"0b11{((p<<1)+q):03b}{z:03b}", 2)] = {
"name": "PUSH AF",
"subins": [
sr_read(sr.index("SP")) | c_qw["addr_inc_en"] | c_qw["addr_dec"] | sr_write(sr.index("SP")),
sr_read(sr.index("SP")) | mr_read(r.index("A")) | mem_write,
sr_read(sr.index("SP")) | c_qw["addr_inc_en"] | c_qw["addr_dec"] | sr_write(sr.index("SP")),
sr_read(sr.index("SP")) | c_qw["F_read_en"] | mem_write | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
z = 5
q = 1
p = 0
instructions[int(f"0b11{((p<<1)+q):03b}{z:03b}", 2)] = {
"name": "CALL nn",
"subins": [
sr_read(sr.index("PC")) | mem_read | sr_write(sr.index("Z")),
sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
sr_read(sr.index("PC")) | mem_read | sr_write(sr.index("W")),
sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
sr_read(sr.index("SP")) | c_qw["addr_inc_en"] | c_qw["addr_dec"] | sr_write(sr.index("SP")),
sr_read(sr.index("PCH")) | c_qw["TMP_write_en"],
sr_read(sr.index("SP")) | tmp_to_db | mem_write,
sr_read(sr.index("SP")) | c_qw["addr_inc_en"] | c_qw["addr_dec"] | sr_write(sr.index("SP")),
sr_read(sr.index("PCL")) | c_qw["TMP_write_en"],
sr_read(sr.index("SP")) | tmp_to_db | mem_write,
sr_read(sr.index("WZ")) | sr_write(sr.index("PC")) | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
z = 5
q = 1
p = 1
instructions[int(f"0b11{((p<<1)+q):03b}{z:03b}", 2)] = {
"name": "DD",
"subins": [
c_qw["reset_context"],
c_qw["DD_prefix_set"] | c_qw["reset_m_state"]
]
}
z = 5
q = 1
p = 2
instructions[int(f"0b11{((p<<1)+q):03b}{z:03b}", 2)] = {
"name": "ED",
"subins": [
c_qw["reset_context"],
c_qw["ED_prefix_set"] | c_qw["reset_m_state"]
]
}
z = 5
q = 1
p = 3
instructions[int(f"0b11{((p<<1)+q):03b}{z:03b}", 2)] = {
"name": "FD",
"subins": [
c_qw["reset_context"],
c_qw["FD_prefix_set"] | c_qw["reset_m_state"]
]
}
z=6
for y in range(8):
if y == 7: continue
instructions[int(f"0b11{y:03b}{z:03b}", 2)] = {
"name": f"{alu[y]} n",
"subins": [
sr_read(sr.index("PC")) | mem_read | c_qw["TMP_write_en"] | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
f_to_flatch,
a_to_acu,
alu_op(y,use_overflow=(y not in (4,5,6))) | mr_write(r.index('A')),
flatch_to_f | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
z = 6
y = 7
instructions[int(f"0b11{y:03b}{z:03b}", 2)] = {
"name": f"CP n",
"subins": [
sr_read(sr.index("PC")) | mem_read | c_qw["TMP_write_en"] | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
f_to_flatch,
a_to_acu,
alu_op(alu.index("SUB")),
flatch_to_f | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}
z = 7
for y in range(8):
instructions[int(f"0b11{y:03b}{z:03b}", 2)] = {
"name": f"RST {y*8:02X}h",
"subins": [
sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | c_qw["addr_dec"] | sr_write(sr.index("PC")),
sr_read(sr.index("PC")) | c_qw["ACU_write_en"] | c_qw["addr_inc_en"] | sr_read(sr.index("PC")),
internal_byte_to_db(internal_byte.index("C7")) | c_qw["TMP_write_en"],
alu_op(alu.index("SUB"),save_flags=False) | sr_write(sr.index("Z")),
sr_write(sr.index("W")),
sr_read(sr.index("WZ")) | sr_write(sr.index("PC")) | c_qw["reset_m_state"] | c_qw["reset_context"]
]
}

256
z80opcodelist.form.txt Normal file
View File

@ -0,0 +1,256 @@
0x00 NOP
0x01 LD BC, nn
0x02 LD (BC), A
0x03 INC BC
0x04 INC B
0x05 DEC B
0x06 LD B, n
0x07 RLCA
0x08 EX AF, AF'
0x09 ADD HL, BC
0x0A LD A, (BC)
0x0B DEC BC
0x0C INC C
0x0D DEC C
0x0E LD C, n
0x0F RRCA
0x10 DJNZ d
0x11 LD DE, nn
0x12 LD (DE), A
0x13 INC DE
0x14 INC D
0x15 DEC D
0x16 LD D, n
0x17 RLA
0x18 JR d
0x19 ADD HL, DE
0x1A LD A, (DE)
0x1B DEC DE
0x1C INC E
0x1D DEC E
0x1E LD E, n
0x1F RRA
0x20 JR NZ, d
0x21 LD HL, nn
0x22 LD (nn), HL
0x23 INC HL
0x24 INC H
0x25 DEC H
0x26 LD H, n
0x27 DAA
0x28 JR Z, d
0x29 ADD HL, HL
0x2A LD HL, (nn)
0x2B DEC HL
0x2C INC L
0x2D DEC L
0x2E LD L, n
0x2F CPL
0x30 JR NC, d
0x31 LD SP, nn
0x32 LD (nn), A
0x33 INC SP
0x34 INC (HL)
0x35 DEC (HL)
0x36 LD (HL), n
0x37 SCF
0x38 JR C, d
0x39 ADD HL, SP
0x3A LD A, (nn)
0x3B DEC SP
0x3C INC A
0x3D DEC A
0x3E LD A, n
0x3F CCF
0x40 LD B, B
0x41 LD B, C
0x42 LD B, D
0x43 LD B, E
0x44 LD B, H
0x45 LD B, L
0x46 LD B, (HL)
0x47 LD B, A
0x48 LD C, B
0x49 LD C, C
0x4A LD C, D
0x4B LD C, E
0x4C LD C, H
0x4D LD C, L
0x4E LD C, (HL)
0x4F LD C, A
0x50 LD D, B
0x51 LD D, C
0x52 LD D, D
0x53 LD D, E
0x54 LD D, H
0x55 LD D, L
0x56 LD D, (HL)
0x57 LD D, A
0x58 LD E, B
0x59 LD E, C
0x5A LD E, D
0x5B LD E, E
0x5C LD E, H
0x5D LD E, L
0x5E LD E, (HL)
0x5F LD E, A
0x60 LD H, B
0x61 LD H, C
0x62 LD H, D
0x63 LD H, E
0x64 LD H, H
0x65 LD H, L
0x66 LD H, (HL)
0x67 LD H, A
0x68 LD L, B
0x69 LD L, C
0x6A LD L, D
0x6B LD L, E
0x6C LD L, H
0x6D LD L, L
0x6E LD L, (HL)
0x6F LD L, A
0x70 LD (HL), B
0x71 LD (HL), C
0x72 LD (HL), D
0x73 LD (HL), E
0x74 LD (HL), H
0x75 LD (HL), L
0x76 HALT
0x77 LD (HL), A
0x78 LD A, B
0x79 LD A, C
0x7A LD A, D
0x7B LD A, E
0x7C LD A, H
0x7D LD A, L
0x7E LD A, (HL)
0x7F LD A, A
0x80 ADD B
0x81 ADD C
0x82 ADD D
0x83 ADD E
0x84 ADD H
0x85 ADD L
0x86 ADD (HL)
0x87 ADD A
0x88 ADC B
0x89 ADC C
0x8A ADC D
0x8B ADC E
0x8C ADC H
0x8D ADC L
0x8E ADC (HL)
0x8F ADC A
0x90 SUB B
0x91 SUB C
0x92 SUB D
0x93 SUB E
0x94 SUB H
0x95 SUB L
0x96 SUB (HL)
0x97 SUB A
0x98 SBC B
0x99 SBC C
0x9A SBC D
0x9B SBC E
0x9C SBC H
0x9D SBC L
0x9E SBC (HL)
0x9F SBC A
0xA0 AND B
0xA1 AND C
0xA2 AND D
0xA3 AND E
0xA4 AND H
0xA5 AND L
0xA6 AND (HL)
0xA7 AND A
0xA8 XOR B
0xA9 XOR C
0xAA XOR D
0xAB XOR E
0xAC XOR H
0xAD XOR L
0xAE XOR (HL)
0xAF XOR A
0xB0 OR B
0xB1 OR C
0xB2 OR D
0xB3 OR E
0xB4 OR H
0xB5 OR L
0xB6 OR (HL)
0xB7 OR A
0xB8 CP B
0xB9 CP C
0xBA CP D
0xBB CP E
0xBC CP H
0xBD CP L
0xBE CP (HL)
0xBF CP A
0xC0 RET NZ
0xC1 POP BC
0xC2 JP NZ, nn
0xC3 JP nn
0xC4 CALL NZ, nn
0xC5 PUSH BC
0xC6 ADD n
0xC7 RST n
0xC8 RET Z
0xC9 RET
0xCA JP Z, nn
0xCB CB
0xCC CALL Z, nn
0xCD CALL nn
0xCE ADC n
0xCF RST
0xD0 RET NC
0xD1 POP DE
0xD2 JP NC, nn
0xD3 OUT (n), A
0xD4 CALL NC, nn
0xD5 PUSH DE
0xD6 SUB n
0xD7 RST
0xD8 RET C
0xD9 EXX
0xDA JP C, nn
0xDB IN A, (n)
0xDC CALL C, nn
0xDD DD
0xDE SBC n
0xDF RST
0xE0 RET PO
0xE1 POP HL
0xE2 JP PO, nn
0xE3 EX (SP), HL
0xE4 CALL PO, nn
0xE5 PUSH HL
0xE6 AND n
0xE7 RST
0xE8 RET PE
0xE9 JP (HL)
0xEA JP PE, nn
0xEB EX DE, HL
0xEC CALL PE, nn
0xED ED
0xEE XOR n
0xEF RST
0xF0 RET P
0xF1 POP AF
0xF2 JP P, nn
0xF3 DI
0xF4 CALL P, nn
0xF5 PUSH AF
0xF6 OR n
0xF7 RST
0xF8 RET M
0xF9 LD SP, HL
0xFA JP M, nn
0xFB EI
0xFC CALL M, nn
0xFD FD
0xFE CP n
0xFF RST

256
z80opcodelist.txt Normal file
View File

@ -0,0 +1,256 @@
00 NOP - RLC B rlc (iy+0)->b MOS_QUIT
01 LD BC,&0000 - RLC C rlc (iy+0)->c MOS_CLI
02 LD (BC),A - RLC D rlc (iy+0)->d MOS_BYTE
03 INC BC - RLC E rlc (iy+0)->e MOS_WORD
04 INC B - RLC H rlc (iy+0)->h MOS_WRCH
05 DEC B - RLC L rlc (iy+0)->l MOS_RDCH
06 LD B,&00 - RLC (HL) RLC (IY+0) MOS_FILE
07 RLCA - RLC A rlc (iy+0)->a MOS_ARGS
08 EX AF,AF' - RRC B rrc (iy+0)->b MOS_BGET
09 ADD HL,BC ADD IX,BC RRC C rrc (iy+0)->c MOS_BPUT
0A LD A,(BC) - RRC D rrc (iy+0)->d MOS_GBPB
0B DEC BC - RRC E rrc (iy+0)->e MOS_FIND
0C INC C - RRC H rrc (iy+0)->h MOS_FF0C
0D DEC C - RRC L rrc (iy+0)->l MOS_FF0D
0E LD C,&00 - RRC (HL) RRC (IY+0) MOS_FF0E
0F RRCA - RRC A rrc (iy+0)->a MOS_FF0F
10 DJNZ &4546 - RL B rl (iy+0)->b -
11 LD DE,&0000 - RL C rl (iy+0)->c -
12 LD (DE),A - RL D rl (iy+0)->d -
13 INC DE - RL E rl (iy+0)->e -
14 INC D - RL H rl (iy+0)->h -
15 DEC D - RL L rl (iy+0)->l -
16 LD D,&00 - RL (HL) RL (IY+0) -
17 RLA - RL A rl (iy+0)->a -
18 JR &4546 - RR B rr (iy+0)->b -
19 ADD HL,DE ADD IX,DE RR C rr (iy+0)->c -
1A LD A,(DE) - RR D rr (iy+0)->d -
1B DEC DE - RR E rr (iy+0)->e -
1C INC E - RR H rr (iy+0)->h -
1D DEC E - RR L rr (iy+0)->l -
1E LD E,&00 - RR (HL) RR (IY+0) -
1F RRA - RR A rr (iy+0)->a -
20 JR NZ,&4546 - SLA B sla (iy+0)->b -
21 LD HL,&0000 LD IX,&0000 SLA C sla (iy+0)->c -
22 LD (&0000),HL LD (&0000),IX SLA D sla (iy+0)->d -
23 INC HL INC IX SLA E sla (iy+0)->e -
24 INC H INC IXH SLA H sla (iy+0)->h -
25 DEC H DEC IXH SLA L sla (iy+0)->l -
26 LD H,&00 LD IXH,&00 SLA (HL) SLA (IY+0) -
27 DAA - SLA A sla (iy+0)->a -
28 JR Z,&4546 - SRA B sra (iy+0)->b -
29 ADD HL,HL ADD IX,IX SRA C sra (iy+0)->c -
2A LD HL,(&0000) LD IX,(&0000) SRA D sra (iy+0)->d -
2B DEC HL DEC IX SRA E sra (iy+0)->e -
2C INC L INC IXL SRA H sra (iy+0)->h -
2D DEC L DEC IXL SRA L sra (iy+0)->l -
2E LD L,&00 LD IXL,&00 SRA (HL) SRA (IY+0) -
2F CPL - SRA A sra (iy+0)->a -
30 JR NC,&4546 - SLS B sls (iy+0)->b -
31 LD SP,&0000 - SLS C sls (iy+0)->c -
32 LD (&0000),A - SLS D sls (iy+0)->d -
33 INC SP - SLS E sls (iy+0)->e -
34 INC (HL) INC (IX+0) SLS H sls (iy+0)->h -
35 DEC (HL) DEC (IX+0) SLS L sls (iy+0)->l -
36 LD (HL),&00 LD (IX+0),&00 SLS (HL) SLS (IY+0) -
37 SCF - SLS A sls (iy+0)->a -
38 JR C,&4546 - SRL B srl (iy+0)->b -
39 ADD HL,SP ADD IX,SP SRL C srl (iy+0)->c -
3A LD A,(&0000) - SRL D srl (iy+0)->d -
3B DEC SP - SRL E srl (iy+0)->e -
3C INC A - SRL H srl (iy+0)->h -
3D DEC A - SRL L srl (iy+0)->l -
3E LD A,&00 - SRL (HL) SRL (IY+0) -
3F CCF - SRL A srl (iy+0)->a -
40 LD B,B - BIT 0,B bit 0,(iy+0)->b IN B,(C)
41 LD B,C - BIT 0,C bit 0,(iy+0)->c OUT (C),B
42 LD B,D - BIT 0,D bit 0,(iy+0)->d SBC HL,BC
43 LD B,E - BIT 0,E bit 0,(iy+0)->e LD (&0000),BC
44 LD B,H LD B,IXH BIT 0,H bit 0,(iy+0)->h NEG
45 LD B,L LD B,IXL BIT 0,L bit 0,(iy+0)->l RETN
46 LD B,(HL) LD B,(IX+0) BIT 0,(HL) BIT 0,(IY+0) IM 0
47 LD B,A - BIT 0,A bit 0,(iy+0)->a LD I,A
48 LD C,B - BIT 1,B bit 1,(iy+0)->b IN C,(C)
49 LD C,C - BIT 1,C bit 1,(iy+0)->c OUT (C),C
4A LD C,D - BIT 1,D bit 1,(iy+0)->d ADC HL,BC
4B LD C,E - BIT 1,E bit 1,(iy+0)->e LD BC,(&0000)
4C LD C,H LD C,IXH BIT 1,H bit 1,(iy+0)->h [neg]
4D LD C,L LD C,IXL BIT 1,L bit 1,(iy+0)->l RETI
4E LD C,(HL) LD C,(IX+0) BIT 1,(HL) BIT 1,(IY+0) [im0]
4F LD C,A - BIT 1,A bit 1,(iy+0)->a LD R,A
50 LD D,B - BIT 2,B bit 2,(iy+0)->b IN D,(C)
51 LD D,C - BIT 2,C bit 2,(iy+0)->c OUT (C),D
52 LD D,D - BIT 2,D bit 2,(iy+0)->d SBC HL,DE
53 LD D,E - BIT 2,E bit 2,(iy+0)->e LD (&0000),DE
54 LD D,H LD D,IXH BIT 2,H bit 2,(iy+0)->h [neg]
55 LD D,L LD D,IXL BIT 2,L bit 2,(iy+0)->l [retn]
56 LD D,(HL) LD D,(IX+0) BIT 2,(HL) BIT 2,(IY+0) IM 1
57 LD D,A - BIT 2,A bit 2,(iy+0)->a LD A,I
58 LD E,B - BIT 3,B bit 3,(iy+0)->b IN E,(C)
59 LD E,C - BIT 3,C bit 3,(iy+0)->c OUT (C),E
5A LD E,D - BIT 3,D bit 3,(iy+0)->d ADC HL,DE
5B LD E,E - BIT 3,E bit 3,(iy+0)->e LD DE,(&0000)
5C LD E,H LD E,IXH BIT 3,H bit 3,(iy+0)->h [neg]
5D LD E,L LD E,IXL BIT 3,L bit 3,(iy+0)->l [reti]
5E LD E,(HL) LD E,(IX+0) BIT 3,(HL) BIT 3,(IY+0) IM 2
5F LD E,A - BIT 3,A bit 3,(iy+0)->a LD A,R
60 LD H,B LD IXH,B BIT 4,B bit 4,(iy+0)->b IN H,(C)
61 LD H,C LD IXH,C BIT 4,C bit 4,(iy+0)->c OUT (C),H
62 LD H,D LD IXH,D BIT 4,D bit 4,(iy+0)->d SBC HL,HL
63 LD H,E LD IXH,E BIT 4,E bit 4,(iy+0)->e LD (&0000),HL
64 LD H,H LD IXH,IXH BIT 4,H bit 4,(iy+0)->h [neg]
65 LD H,L LD IXH,IXL BIT 4,L bit 4,(iy+0)->l [retn]
66 LD H,(HL) LD H,(IX+0) BIT 4,(HL) BIT 4,(IY+0) [im0]
67 LD H,A LD IXH,A BIT 4,A bit 4,(iy+0)->a RRD
68 LD L,B LD IXL,B BIT 5,B bit 5,(iy+0)->b IN L,(C)
69 LD L,C LD IXL,C BIT 5,C bit 5,(iy+0)->c OUT (C),L
6A LD L,D LD IXL,D BIT 5,D bit 5,(iy+0)->d ADC HL,HL
6B LD L,E LD IXL,E BIT 5,E bit 5,(iy+0)->e LD HL,(&0000)
6C LD L,H LD IXL,IXH BIT 5,H bit 5,(iy+0)->h [neg]
6D LD L,L LD IXL,IXL BIT 5,L bit 5,(iy+0)->l [reti]
6E LD L,(HL) LD L,(IX+0) BIT 5,(HL) BIT 5,(IY+0) [im0]
6F LD L,A LD IXL,A BIT 5,A bit 5,(iy+0)->a RLD
70 LD (HL),B LD (IX+0),B BIT 6,B bit 6,(iy+0)->b IN F,(C)
71 LD (HL),C LD (IX+0),C BIT 6,C bit 6,(iy+0)->c OUT (C),F
72 LD (HL),D LD (IX+0),D BIT 6,D bit 6,(iy+0)->d SBC HL,SP
73 LD (HL),E LD (IX+0),E BIT 6,E bit 6,(iy+0)->e LD (&0000),SP
74 LD (HL),H LD (IX+0),H BIT 6,H bit 6,(iy+0)->h [neg]
75 LD (HL),L LD (IX+0),L BIT 6,L bit 6,(iy+0)->l [retn]
76 HALT - BIT 6,(HL) BIT 6,(IY+0) [im1]
77 LD (HL),A LD (IX+0),A BIT 6,A bit 6,(iy+0)->a [ld i,i?]
78 LD A,B - BIT 7,B bit 7,(iy+0)->b IN A,(C)
79 LD A,C - BIT 7,C bit 7,(iy+0)->c OUT (C),A
7A LD A,D - BIT 7,D bit 7,(iy+0)->d ADC HL,SP
7B LD A,E - BIT 7,E bit 7,(iy+0)->e LD SP,(&0000)
7C LD A,H LD A,IXH BIT 7,H bit 7,(iy+0)->h [neg]
7D LD A,L LD A,IXL BIT 7,L bit 7,(iy+0)->l [reti]
7E LD A,(HL) LD A,(IX+0) BIT 7,(HL) BIT 7,(IY+0) [im2]
7F LD A,A - BIT 7,A bit 7,(iy+0)->a [ld r,r?]
80 ADD A,B - RES 0,B res 0,(iy+0)->b -
81 ADD A,C - RES 0,C res 0,(iy+0)->c -
82 ADD A,D - RES 0,D res 0,(iy+0)->d -
83 ADD A,E - RES 0,E res 0,(iy+0)->e -
84 ADD A,H ADD A,IXH RES 0,H res 0,(iy+0)->h -
85 ADD A,L ADD A,IXL RES 0,L res 0,(iy+0)->l -
86 ADD A,(HL) ADD A,(IX+0) RES 0,(HL) RES 0,(IY+0) -
87 ADD A,A - RES 0,A res 0,(iy+0)->a -
88 ADC A,B - RES 1,B res 1,(iy+0)->b -
89 ADC A,C - RES 1,C res 1,(iy+0)->c -
8A ADC A,D - RES 1,D res 1,(iy+0)->d -
8B ADC A,E - RES 1,E res 1,(iy+0)->e -
8C ADC A,H ADC A,IXH RES 1,H res 1,(iy+0)->h -
8D ADC A,L ADC A,IXL RES 1,L res 1,(iy+0)->l -
8E ADC A,(HL) ADC A,(IX+0) RES 1,(HL) RES 1,(IY+0) -
8F ADC A,A - RES 1,A res 1,(iy+0)->a -
90 SUB A,B - RES 2,B res 2,(iy+0)->b -
91 SUB A,C - RES 2,C res 2,(iy+0)->c -
92 SUB A,D - RES 2,D res 2,(iy+0)->d -
93 SUB A,E - RES 2,E res 2,(iy+0)->e -
94 SUB A,H SUB A,IXH RES 2,H res 2,(iy+0)->h -
95 SUB A,L SUB A,IXL RES 2,L res 2,(iy+0)->l -
96 SUB A,(HL) SUB A,(IX+0) RES 2,(HL) RES 2,(IY+0) -
97 SUB A,A - RES 2,A res 2,(iy+0)->a -
98 SBC A,B - RES 3,B res 3,(iy+0)->b -
99 SBC A,C - RES 3,C res 3,(iy+0)->c -
9A SBC A,D - RES 3,D res 3,(iy+0)->d -
9B SBC A,E - RES 3,E res 3,(iy+0)->e -
9C SBC A,H SBC A,IXH RES 3,H res 3,(iy+0)->h -
9D SBC A,L SBC A,IXL RES 3,L res 3,(iy+0)->l -
9E SBC A,(HL) SBC A,(IX+0) RES 3,(HL) RES 3,(IY+0) -
9F SBC A,A - RES 3,A res 3,(iy+0)->a -
A0 AND B - RES 4,B res 4,(iy+0)->b LDI
A1 AND C - RES 4,C res 4,(iy+0)->c CPI
A2 AND D - RES 4,D res 4,(iy+0)->d INI
A3 AND E - RES 4,E res 4,(iy+0)->e OTI
A4 AND H AND IXH RES 4,H res 4,(iy+0)->h -
A5 AND L AND IXL RES 4,L res 4,(iy+0)->l -
A6 AND (HL) AND (IX+0) RES 4,(HL) RES 4,(IY+0) -
A7 AND A - RES 4,A res 4,(iy+0)->a -
A8 XOR B - RES 5,B res 5,(iy+0)->b LDD
A9 XOR C - RES 5,C res 5,(iy+0)->c CPD
AA XOR D - RES 5,D res 5,(iy+0)->d IND
AB XOR E - RES 5,E res 5,(iy+0)->e OTD
AC XOR H XOR IXH RES 5,H res 5,(iy+0)->h -
AD XOR L XOR IXL RES 5,L res 5,(iy+0)->l -
AE XOR (HL) XOR (IX+0) RES 5,(HL) RES 5,(IY+0) -
AF XOR A - RES 5,A res 5,(iy+0)->a -
B0 OR B - RES 6,B res 6,(iy+0)->b LDIR
B1 OR C - RES 6,C res 6,(iy+0)->c CPIR
B2 OR D - RES 6,D res 6,(iy+0)->d INIR
B3 OR E - RES 6,E res 6,(iy+0)->e OTIR
B4 OR H OR IXH RES 6,H res 6,(iy+0)->h -
B5 OR L OR IXL RES 6,L res 6,(iy+0)->l -
B6 OR (HL) OR (IX+0) RES 6,(HL) RES 6,(IY+0) -
B7 OR A - RES 6,A res 6,(iy+0)->a -
B8 CP B - RES 7,B res 7,(iy+0)->b LDDR
B9 CP C - RES 7,C res 7,(iy+0)->c CPDR
BA CP D - RES 7,D res 7,(iy+0)->d INDR
BB CP E - RES 7,E res 7,(iy+0)->e OTDR
BC CP H CP IXH RES 7,H res 7,(iy+0)->h -
BD CP L CP IXL RES 7,L res 7,(iy+0)->l -
BE CP (HL) CP (IX+0) RES 7,(HL) RES 7,(IY+0) -
BF CP A - RES 7,A res 7,(iy+0)->a -
C0 RET NZ - SET 0,B set 0,(iy+0)->b -
C1 POP BC - SET 0,C set 0,(iy+0)->c -
C2 JP NZ,&0000 - SET 0,D set 0,(iy+0)->d -
C3 JP &0000 - SET 0,E set 0,(iy+0)->e -
C4 CALL NZ,&0000 - SET 0,H set 0,(iy+0)->h -
C5 PUSH BC - SET 0,L set 0,(iy+0)->l -
C6 ADD A,&00 - SET 0,(HL) SET 0,(IY+0) -
C7 RST &00 - SET 0,A set 0,(iy+0)->a -
C8 RET Z - SET 1,B set 1,(iy+0)->b -
C9 RET - SET 1,C set 1,(iy+0)->c -
CA JP Z,&0000 - SET 1,D set 1,(iy+0)->d -
CB **** CB **** - SET 1,E set 1,(iy+0)->e -
CC CALL Z,&0000 - SET 1,H set 1,(iy+0)->h -
CD CALL &0000 - SET 1,L set 1,(iy+0)->l -
CE ADC A,&00 - SET 1,(HL) SET 1,(IY+0) -
CF RST &08 - SET 1,A set 1,(iy+0)->a -
D0 RET NC - SET 2,B set 2,(iy+0)->b -
D1 POP DE - SET 2,C set 2,(iy+0)->c -
D2 JP NC,&0000 - SET 2,D set 2,(iy+0)->d -
D3 OUT (&00),A - SET 2,E set 2,(iy+0)->e -
D4 CALL NC,&0000 - SET 2,H set 2,(iy+0)->h -
D5 PUSH DE - SET 2,L set 2,(iy+0)->l -
D6 SUB A,&00 - SET 2,(HL) SET 2,(IY+0) -
D7 RST &10 - SET 2,A set 2,(iy+0)->a -
D8 RET C - SET 3,B set 3,(iy+0)->b -
D9 EXX - SET 3,C set 3,(iy+0)->c -
DA JP C,&0000 - SET 3,D set 3,(iy+0)->d -
DB IN A,(&00) - SET 3,E set 3,(iy+0)->e -
DC CALL C,&0000 - SET 3,H set 3,(iy+0)->h -
DD **** DD **** - SET 3,L set 3,(iy+0)->l -
DE SBC A,&00 - SET 3,(HL) SET 3,(IY+0) -
DF RST &18 - SET 3,A set 3,(iy+0)->a -
E0 RET PO - SET 4,B set 4,(iy+0)->b -
E1 POP HL POP IX SET 4,C set 4,(iy+0)->c -
E2 JP PO,&0000 - SET 4,D set 4,(iy+0)->d -
E3 EX (SP),HL EX (SP),IX SET 4,E set 4,(iy+0)->e -
E4 CALL PO,&0000 - SET 4,H set 4,(iy+0)->h -
E5 PUSH HL PUSH IX SET 4,L set 4,(iy+0)->l -
E6 AND &00 - SET 4,(HL) SET 4,(IY+0) -
E7 RST &20 - SET 4,A set 4,(iy+0)->a -
E8 RET PE - SET 5,B set 5,(iy+0)->b -
E9 JP (HL) JP (IX) SET 5,C set 5,(iy+0)->c -
EA JP PE,&0000 - SET 5,D set 5,(iy+0)->d -
EB EX DE,HL - SET 5,E set 5,(iy+0)->e -
EC CALL PE,&0000 - SET 5,H set 5,(iy+0)->h -
ED **** ED **** - SET 5,L set 5,(iy+0)->l -
EE XOR &00 - SET 5,(HL) SET 5,(IY+0) -
EF RST &28 - SET 5,A set 5,(iy+0)->a -
F0 RET P - SET 6,B set 6,(iy+0)->b -
F1 POP AF - SET 6,C set 6,(iy+0)->c -
F2 JP P,&0000 - SET 6,D set 6,(iy+0)->d -
F3 DI - SET 6,E set 6,(iy+0)->e -
F4 CALL P,&0000 - SET 6,H set 6,(iy+0)->h -
F5 PUSH AF - SET 6,L set 6,(iy+0)->l -
F6 OR &00 - SET 6,(HL) SET 6,(IY+0) -
F7 RST &30 - SET 6,A set 6,(iy+0)->a -
F8 RET M - SET 7,B set 7,(iy+0)->b [z80]
F9 LD SP,HL - SET 7,C set 7,(iy+0)->c [z80]
FA JP M,&0000 - SET 7,D set 7,(iy+0)->d [z80]
FB EI - SET 7,E set 7,(iy+0)->e ED_LOAD
FC CALL M,&0000 - SET 7,H set 7,(iy+0)->h [z80]
FD **** FD **** - SET 7,L set 7,(iy+0)->l [z80]
FE CP &00 - SET 7,(HL) SET 7,(IY+0) [z80]
FF RST &38 - SET 7,A set 7,(iy+0)->a ED_DOS

132
z80shortcuts.py Normal file
View File

@ -0,0 +1,132 @@
# TABLES
c_pins = [
"reset_context",
"reset_m_state",
"HALT+",
"MREQ+",
"IOREQ+",
"RD+",
"WR+",
"",
"IR_write_en",
"DE_HL_tgl",
"shadow_reg_tgl",
"AF_toggle",
"",
"",
"sr_read_en",
"sr_write_en",
"mr_read_en",
"mr_read_0",
"mr_read_1",
"mr_read_2",
"mr_write_en",
"mr_write_0",
"mr_write_1",
"mr_write_2",
"sr_read_0",
"sr_read_1",
"sr_read_2",
"sr_read_3",
"sr_write_0",
"sr_write_1",
"sr_write_2",
"sr_write_3",
"F_read_en",
"F_write_en",
"ACU_write_en",
"TMP_write_en",
"Flatch_read_en",
"Flatch_write_en",
"Flatch_write_from_DB",
"alu_f_use_overflow",
"alu_dev_0",
"alu_dev_1",
"alu_dev_2",
"alu_op_0",
"alu_op_1",
"alu_op_2",
"alu_op_3",
"alu_op_4",
"alu_en",
"addr_inc_en",
"addr_dec",
"internal_byte_to_db_en",
"internal_byte_0",
"",
"",
"exec_if_context",
"exec_if_cond",
"cond_0",
"cond_1",
"cond_2",
"CB_prefix_set",
"ED_prefix_set",
"DD_prefix_set",
"FD_prefix_set",
]
c_qw = {}
for pin in c_pins:
#print(pin, 2**c_pins.index(pin))
c_qw[pin] = 2**c_pins.index(pin)
r = ['B', 'C', 'D', 'E', 'H', 'L', '(HL)', 'A']
rp = ['BC', 'DE', 'HL', 'SP']
rp2 = ['BC', 'DE', 'HL', 'AF']
sr = ['SPH','SPL','SP','W','Z','WZ','PCH','PCL','PC']
cc = ["NZ", "Z", "NC", "C", "PO", "PE", "P", "M"]
cc_i = {"NZ":1, "Z":0, "NC":3, "C":2, "PO":5, "PE":4, "P":7, "M":6}
flags = ["C","N","P/V","F3","H","F5","Z","S"]
alu_dev = ["ALU", "SLU", "INC", "BMU", "SLUA", "DAA"]
alu = ["ADD", "ADC", "SUB", "SBC", "AND", "XOR", "OR", "NOT"]
rot = ["RLC", "RRC", "RL", "RR", "SLA", "SRA", "SLL", "SRL", "RRD","","","","RLD"]
inc = ["PASS","INC", "", "DEC"]
bit = {"SET": 16, "RESET": 8}
bli = {
4: ["LDI", "CPI", "INI", "OUTI"],
5: ["LDD", "CPD", "IND", "OUTD"],
6: ["LDIR", "CPIR", "INIR", "OTIR"],
7: ["LDDR", "CPDR", "INDR", "OTDR"]
}
internal_byte = ["FF", "C7"]
def exec_if_cond(c_code):
return c_qw["exec_if_cond"] | (c_code << c_pins.index("cond_0"))
def internal_byte_to_db(byte_code):
return c_qw["internal_byte_to_db_en"] | (byte_code << c_pins.index("internal_byte_0"))
def mr_read(register_index):
return c_qw["mr_read_en"] | (register_index << c_pins.index("mr_read_0"))
def mr_write(register_index):
return c_qw["mr_write_en"] | (register_index << c_pins.index("mr_write_0"))
def sr_read(register_index):
return c_qw["sr_read_en"] | (register_index << c_pins.index("sr_read_0"))
def sr_write(register_index):
return c_qw["sr_write_en"] | (register_index << c_pins.index("sr_write_0"))
def alu_op(op,dev=0,save_flags=True,use_overflow=True):
return (dev << c_pins.index("alu_dev_0")) | (op << c_pins.index("alu_op_0")) | c_qw["alu_en"] | (0, c_qw["alu_f_use_overflow"])[use_overflow] | (0, c_qw["Flatch_write_en"])[save_flags]
def cp_bit(index):
return (alu_dev.index("BMU") << c_pins.index("alu_dev_0")) | (index << c_pins.index("alu_op_0")) | c_qw["alu_f_use_overflow"] | c_qw["Flatch_write_en"]
def set_bit(index):
return (alu_dev.index("BMU") << c_pins.index("alu_dev_0")) | (index << c_pins.index("alu_op_0")) | (bit["SET"] << c_pins.index("alu_op_0")) | c_qw["alu_en"]
def reset_bit(index):
return (alu_dev.index("BMU") << c_pins.index("alu_dev_0")) | (index << c_pins.index("alu_op_0")) | (bit["RESET"] << c_pins.index("alu_op_0")) | c_qw["alu_en"]
nop = 0
inc_pc = sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC"))
clear_flatch = c_qw["Flatch_write_from_DB"] | c_qw["Flatch_write_en"]
f_to_flatch = c_qw["F_read_en"] | c_qw["Flatch_write_from_DB"] | c_qw["Flatch_write_en"]
flatch_to_f = c_qw["Flatch_read_en"] | c_qw["F_write_en"]
f_to_tmp = c_qw["F_read_en"] | c_qw["TMP_write_en"]
f_to_acu = c_qw["F_read_en"] | c_qw["ACU_write_en"]
clear_acu = c_qw["ACU_write_en"]
clear_tmp = c_qw["TMP_write_en"]
a_to_acu = mr_read(r.index("A")) | c_qw["ACU_write_en"]
tmp_to_db = alu_op(0,alu_dev.index("INC"),False) #super hacky
mem_read = c_qw["MREQ+"] | c_qw["RD+"]
mem_write = c_qw["MREQ+"] | c_qw["WR+"]
io_read = c_qw["IOREQ+"] | c_qw["RD+"]
io_write = c_qw["IOREQ+"] | c_qw["WR+"]
exec_if_context = c_qw["exec_if_context"]