# TABLES c_pins = [ "reset_context", "reset_m_state", "HALT+", "MREQ+", "IOREQ+", "RD+", "WR+", "", "IR_write_en", "DE_HL_tgl", "shadow_reg_tgl", "AF_toggle", "", "", "sr_read_en", "sr_write_en", "mr_read_en", "mr_read_0", "mr_read_1", "mr_read_2", "mr_write_en", "mr_write_0", "mr_write_1", "mr_write_2", "sr_read_0", "sr_read_1", "sr_read_2", "sr_read_3", "sr_write_0", "sr_write_1", "sr_write_2", "sr_write_3", "F_read_en", "F_write_en", "ACU_write_en", "TMP_write_en", "Flatch_read_en", "Flatch_write_en", "Flatch_write_from_DB", "alu_f_use_overflow", "alu_dev_0", "alu_dev_1", "alu_dev_2", "alu_op_0", "alu_op_1", "alu_op_2", "alu_op_3", "alu_op_4", "alu_en", "addr_inc_en", "addr_dec", "internal_byte_to_db_en", "internal_byte_0", "", "", "exec_if_context", "exec_if_cond", "cond_0", "cond_1", "cond_2", "CB_prefix_set", "ED_prefix_set", "DD_prefix_set", "FD_prefix_set", ] c_qw = {} for pin in c_pins: #print(pin, 2**c_pins.index(pin)) c_qw[pin] = 2**c_pins.index(pin) r = ['B', 'C', 'D', 'E', 'H', 'L', '(HL)', 'A'] rp = ['BC', 'DE', 'HL', 'SP'] rp2 = ['BC', 'DE', 'HL', 'AF'] sr = ['SPH','SPL','SP','W','Z','WZ','PCH','PCL','PC'] cc = ["NZ", "Z", "NC", "C", "PO", "PE", "P", "M"] cc_i = {"NZ":1, "Z":0, "NC":3, "C":2, "PO":5, "PE":4, "P":7, "M":6} flags = ["C","N","P/V","F3","H","F5","Z","S"] alu_dev = ["ALU", "SLU", "INC", "BMU", "SLUA", "DAA"] alu = ["ADD", "ADC", "SUB", "SBC", "AND", "XOR", "OR", "NOT"] rot = ["RLC", "RRC", "RL", "RR", "SLA", "SRA", "SLL", "SRL", "RRD","","","","RLD"] inc = ["PASS","INC", "", "DEC"] bit = {"SET": 16, "RESET": 8} bli = { 4: ["LDI", "CPI", "INI", "OUTI"], 5: ["LDD", "CPD", "IND", "OUTD"], 6: ["LDIR", "CPIR", "INIR", "OTIR"], 7: ["LDDR", "CPDR", "INDR", "OTDR"] } internal_byte = ["FF", "C7"] def exec_if_cond(c_code): return c_qw["exec_if_cond"] | (c_code << c_pins.index("cond_0")) def internal_byte_to_db(byte_code): return c_qw["internal_byte_to_db_en"] | (byte_code << c_pins.index("internal_byte_0")) def mr_read(register_index): return c_qw["mr_read_en"] | (register_index << c_pins.index("mr_read_0")) def mr_write(register_index): return c_qw["mr_write_en"] | (register_index << c_pins.index("mr_write_0")) def sr_read(register_index): return c_qw["sr_read_en"] | (register_index << c_pins.index("sr_read_0")) def sr_write(register_index): return c_qw["sr_write_en"] | (register_index << c_pins.index("sr_write_0")) def alu_op(op,dev=0,save_flags=True,use_overflow=True): return (dev << c_pins.index("alu_dev_0")) | (op << c_pins.index("alu_op_0")) | c_qw["alu_en"] | (0, c_qw["alu_f_use_overflow"])[use_overflow] | (0, c_qw["Flatch_write_en"])[save_flags] def cp_bit(index): return (alu_dev.index("BMU") << c_pins.index("alu_dev_0")) | (index << c_pins.index("alu_op_0")) | c_qw["alu_f_use_overflow"] | c_qw["Flatch_write_en"] def set_bit(index): return (alu_dev.index("BMU") << c_pins.index("alu_dev_0")) | (index << c_pins.index("alu_op_0")) | (bit["SET"] << c_pins.index("alu_op_0")) | c_qw["alu_en"] def reset_bit(index): return (alu_dev.index("BMU") << c_pins.index("alu_dev_0")) | (index << c_pins.index("alu_op_0")) | (bit["RESET"] << c_pins.index("alu_op_0")) | c_qw["alu_en"] nop = 0 inc_pc = sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")) clear_flatch = c_qw["Flatch_write_from_DB"] | c_qw["Flatch_write_en"] f_to_flatch = c_qw["F_read_en"] | c_qw["Flatch_write_from_DB"] | c_qw["Flatch_write_en"] flatch_to_f = c_qw["Flatch_read_en"] | c_qw["F_write_en"] f_to_tmp = c_qw["F_read_en"] | c_qw["TMP_write_en"] f_to_acu = c_qw["F_read_en"] | c_qw["ACU_write_en"] clear_acu = c_qw["ACU_write_en"] clear_tmp = c_qw["TMP_write_en"] a_to_acu = mr_read(r.index("A")) | c_qw["ACU_write_en"] tmp_to_db = alu_op(0,alu_dev.index("INC"),False) #super hacky mem_read = c_qw["MREQ+"] | c_qw["RD+"] mem_write = c_qw["MREQ+"] | c_qw["WR+"] io_read = c_qw["IOREQ+"] | c_qw["RD+"] io_write = c_qw["IOREQ+"] | c_qw["WR+"] exec_if_context = c_qw["exec_if_context"]