590 lines
23 KiB
Python
590 lines
23 KiB
Python
from z80shortcuts import *
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instructions = [None] * 256
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y = 0
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z = 0
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instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
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"name": "NOP",
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"subins": [
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c_qw["reset_m_state"] | c_qw["reset_context"]
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]
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}
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y = 1
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z = 0
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instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
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"name": "EX AF, AF'",
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"subins": [
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c_qw["AF_toggle"] | c_qw["reset_m_state"] | c_qw["reset_context"]
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]
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}
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y = 2
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z = 0
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instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
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"name": "DJNZ d",
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"subins": [
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sr_read(sr.index("PC")) | mem_read | c_qw["ACU_write_en"] | c_qw["TMP_write_en"] | sr_write(sr.index("Z")),
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sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
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#sign extend
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alu_op(alu.index("ADD")),
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alu_op(alu.index("SBC")) | sr_write(sr.index("W")),
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sr_read(sr.index("PCL")) | c_qw["ACU_write_en"],
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sr_read(sr.index("Z")) | c_qw["TMP_write_en"],
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alu_op(alu.index("ADD")) | sr_write(sr.index("Z")),
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sr_read(sr.index("PCH")) | c_qw["ACU_write_en"],
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sr_read(sr.index("W")) | c_qw["TMP_write_en"],
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alu_op(alu.index("ADC")) | sr_write(sr.index("W")),
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clear_acu,
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mr_read(r.index("B")) | c_qw["TMP_write_en"],
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alu_op(inc.index("DEC"),alu_dev.index("INC")) | mr_write(r.index("B")),
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exec_if_cond(cc_i["NZ"]) | c_qw["reset_m_state"] | c_qw["reset_context"],
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sr_read(sr.index("WZ")) | sr_write(sr.index("PC")) | c_qw["reset_m_state"] | c_qw["reset_context"]
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]
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}
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y = 3
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z = 0
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instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
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"name": "JR d",
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"subins": [
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sr_read(sr.index("PC")) | mem_read | c_qw["ACU_write_en"] | c_qw["TMP_write_en"] | sr_write(sr.index("Z")),
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sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
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#sign extend
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alu_op(alu.index("ADD")),
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alu_op(alu.index("SBC")) | sr_write(sr.index("W")),
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sr_read(sr.index("PCL")) | c_qw["ACU_write_en"],
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sr_read(sr.index("Z")) | c_qw["TMP_write_en"],
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alu_op(alu.index("ADD")) | sr_write(sr.index("Z")),
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sr_read(sr.index("PCH")) | c_qw["ACU_write_en"],
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sr_read(sr.index("W")) | c_qw["TMP_write_en"],
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alu_op(alu.index("ADC")) | sr_write(sr.index("W")),
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sr_read(sr.index("WZ")) | sr_write(sr.index("PC")) | c_qw["reset_m_state"] | c_qw["reset_context"]
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]
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}
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z = 0
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for y in [4, 5, 6, 7]:
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instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
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"name": f"JR {cc[y-4]}, d",
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"subins": [
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sr_read(sr.index("PC")) | mem_read | c_qw["ACU_write_en"] | c_qw["TMP_write_en"] | sr_write(sr.index("Z")),
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sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
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#early return
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f_to_flatch,
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exec_if_cond(cc_i[cc[(y-4)]]) | c_qw["reset_m_state"] | c_qw["reset_context"],
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#sign extend
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alu_op(alu.index("ADD")),
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alu_op(alu.index("SBC")) | sr_write(sr.index("W")),
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sr_read(sr.index("PCL")) | c_qw["ACU_write_en"],
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sr_read(sr.index("Z")) | c_qw["TMP_write_en"], # unneeded
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alu_op(alu.index("ADD")) | sr_write(sr.index("Z")),
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sr_read(sr.index("PCH")) | c_qw["ACU_write_en"],
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sr_read(sr.index("W")) | c_qw["TMP_write_en"],
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alu_op(alu.index("ADC")) | sr_write(sr.index("W")),
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sr_read(sr.index("WZ")) | sr_write(sr.index("PC")) | c_qw["reset_m_state"] | c_qw["reset_context"]
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]
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}
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z = 1
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for y in range(8):
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p = y >> 1
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q = y & 1
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if q != 0: continue
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if p == 3: continue
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instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
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"name": f"LD {rp[p]}, nn",
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"subins": [
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sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")) | mem_read | mr_write((p<<1)+1),
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sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")) | mem_read | mr_write((p<<1)) | c_qw["reset_m_state"] | c_qw["reset_context"]
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]
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}
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z = 1
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y = 6
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instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
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"name": f"LD SP, nn",
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"subins": [
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sr_read(sr.index("PC")) | mem_read | sr_write(sr.index("SPL")),
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sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
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sr_read(sr.index("PC")) | mem_read | sr_write(sr.index("SPH")),
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sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")) | c_qw["reset_m_state"] | c_qw["reset_context"]
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]
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}
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z = 1
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for y in range(8):
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p = y >> 1
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q = y & 1
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if q == 0: continue
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if p == 3: continue
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instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
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"name": f"ADD HL, {rp[p]}",
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"subins": [
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mr_read(r.index("L")) | c_qw["ACU_write_en"],
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mr_read((p<<1)+1) | c_qw["TMP_write_en"],
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alu_op(alu.index("ADD")) | mr_write(r.index("L")),
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mr_read(r.index("H")) | c_qw["ACU_write_en"],
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mr_read((p<<1)) | c_qw["TMP_write_en"],
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alu_op(alu.index("ADC")) | mr_write(r.index("H")),
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flatch_to_f | c_qw["reset_m_state"] | c_qw["reset_context"]
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]
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}
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z = 1
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p = rp.index("SP")
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q = 1
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instructions[int(f"0b00{((p<<1)+q):03b}{z:03b}", 2)] = {
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"name": f"ADD HL, SP",
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"subins": [
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mr_read(r.index("L")) | c_qw["ACU_write_en"],
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sr_read(sr.index("SPL")) | c_qw["TMP_write_en"],
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alu_op(alu.index("ADD")) | mr_write(r.index("L")),
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mr_read(r.index("H")) | c_qw["ACU_write_en"],
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sr_read(sr.index("SPH")) | c_qw["TMP_write_en"],
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alu_op(alu.index("ADC")) | mr_write(r.index("H")),
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flatch_to_f | c_qw["reset_m_state"] | c_qw["reset_context"]
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]
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}
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z = 2
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q = 0
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p = 0
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instructions[int(f"0b00{((p<<1)+q):03b}{z:03b}", 2)] = {
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"name": f"LD (BC), A",
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"subins": [
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mr_read(r.index("B")) | sr_write(sr.index("W")),
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mr_read(r.index("C")) | sr_write(sr.index("Z")),
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sr_read(sr.index("WZ")) | mr_read(r.index("A")) | mem_write | c_qw["reset_m_state"] | c_qw["reset_context"]
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]
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}
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z = 2
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q = 0
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p = 1
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instructions[int(f"0b00{((p<<1)+q):03b}{z:03b}", 2)] = {
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"name": f"LD (DE), A",
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"subins": [
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mr_read(r.index("D")) | sr_write(sr.index("W")),
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mr_read(r.index("E")) | sr_write(sr.index("Z")),
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sr_read(sr.index("WZ")) | mr_read(r.index("A")) | mem_write | c_qw["reset_m_state"] | c_qw["reset_context"]
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]
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}
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z = 2
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q = 0
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p = 2
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instructions[int(f"0b00{((p<<1)+q):03b}{z:03b}", 2)] = {
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"name": f"LD (nn), HL",
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"subins": [
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sr_read(sr.index("PC")) | mem_read | sr_write(sr.index("Z")),
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sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
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sr_read(sr.index("PC")) | mem_read | sr_write(sr.index("W")),
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sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
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sr_read(sr.index("WZ")) | mr_read(r.index("L")) | mem_write | c_qw["addr_inc_en"] | sr_write(sr.index("WZ")),
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sr_read(sr.index("WZ")) | mr_read(r.index("H")) | mem_write | c_qw["reset_m_state"] | c_qw["reset_context"]
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]
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}
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z = 2
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q = 0
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p = 3
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instructions[int(f"0b00{((p<<1)+q):03b}{z:03b}", 2)] = {
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"name": f"LD (nn), A",
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"subins": [
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sr_read(sr.index("PC")) | mem_read | sr_write(sr.index("Z")),
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sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
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sr_read(sr.index("PC")) | mem_read | sr_write(sr.index("W")),
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sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
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sr_read(sr.index("WZ")) | mr_read(r.index("A")) | mem_write | c_qw["reset_m_state"] | c_qw["reset_context"]
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]
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}
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z = 2
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q = 1
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p = 0
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instructions[int(f"0b00{((p<<1)+q):03b}{z:03b}", 2)] = {
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"name": f"LD A, (BC)",
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"subins": [
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mr_read(r.index("B")) | sr_write(sr.index("W")),
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mr_read(r.index("C")) | sr_write(sr.index("Z")),
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sr_read(sr.index("WZ")) | mem_read | mr_write(r.index("A")) | c_qw["reset_m_state"] | c_qw["reset_context"]
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]
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}
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z = 2
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q = 1
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p = 1
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instructions[int(f"0b00{((p<<1)+q):03b}{z:03b}", 2)] = {
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"name": f"LD A, (DE)",
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"subins": [
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mr_read(r.index("D")) | sr_write(sr.index("W")),
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mr_read(r.index("E")) | sr_write(sr.index("Z")),
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sr_read(sr.index("WZ")) | mem_read | mr_write(r.index("A")) | c_qw["reset_m_state"] | c_qw["reset_context"]
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]
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}
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z = 2
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q = 1
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p = 2
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instructions[int(f"0b00{((p<<1)+q):03b}{z:03b}", 2)] = {
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"name": f"LD HL, (nn)",
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"subins": [
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sr_read(sr.index("PC")) | mem_read |sr_write(sr.index("Z")),
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sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
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sr_read(sr.index("PC")) | mem_read | sr_write(sr.index("W")),
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sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
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sr_read(sr.index("WZ")) | mem_read | mr_write(r.index("L")),
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sr_read(sr.index("WZ")) | c_qw["addr_inc_en"] | sr_write(sr.index("WZ")),
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sr_read(sr.index("WZ")) | mem_read | mr_write(r.index("H")) | c_qw["reset_m_state"] | c_qw["reset_context"]
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]
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}
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z = 2
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q = 1
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p = 3
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instructions[int(f"0b00{((p<<1)+q):03b}{z:03b}", 2)] = {
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"name": f"LD A, (nn)",
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"subins": [
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sr_read(sr.index("PC")) | mem_read | sr_write(sr.index("Z")),
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sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
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sr_read(sr.index("PC")) | mem_read | sr_write(sr.index("W")),
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sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
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sr_read(sr.index("WZ")) | mem_read | mr_write(r.index("A")) | c_qw["reset_m_state"] | c_qw["reset_context"]
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]
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}
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z = 3
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q = 0
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for p in range(3):
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instructions[int(f"0b00{((p<<1)+q):03b}{z:03b}", 2)] = {
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"name": f"INC {rp[p]}",
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"subins": [
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clear_acu,
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mr_read((p<<1)+1) | c_qw["TMP_write_en"],
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alu_op(inc.index("INC"),alu_dev.index("INC")) | mr_write((p<<1)+1),
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mr_read((p<<1)) | c_qw["TMP_write_en"],
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alu_op(alu.index("ADC")) | mr_write((p<<1)) | c_qw["reset_m_state"] | c_qw["reset_context"]
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]
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}
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z = 3
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q = 0
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p = rp.index("SP")
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instructions[int(f"0b00{((p<<1)+q):03b}{z:03b}", 2)] = {
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"name": f"INC SP",
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"subins": [
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clear_acu,
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sr_read(sr.index("SPL")) | c_qw["TMP_write_en"],
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alu_op(inc.index("INC"),alu_dev.index("INC")) | sr_write(sr.index("SPL")),
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sr_read(sr.index("SPH")) | c_qw["TMP_write_en"],
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alu_op(alu.index("ADC")) | sr_write(sr.index("SPH")) | c_qw["reset_m_state"] | c_qw["reset_context"]
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]
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}
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z = 3
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q = 1
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for p in range(2):
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instructions[int(f"0b00{((p<<1)+q):03b}{z:03b}", 2)] = {
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"name": f"DEC {rp[p]}",
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"subins": [
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clear_acu,
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mr_read((p<<1)+1) | c_qw["TMP_write_en"],
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alu_op(inc.index("DEC"),alu_dev.index("INC")) | mr_write((p<<1)+1),
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clear_tmp,
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mr_read((p<<1)) | c_qw["ACU_write_en"],
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alu_op(alu.index("SBC")) | mr_write((p<<1)) | c_qw["reset_m_state"] | c_qw["reset_context"]
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]
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}
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z = 3
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q = 1
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p = rp.index("SP")
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instructions[int(f"0b00{((p<<1)+q):03b}{z:03b}", 2)] = {
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"name": f"DEC SP",
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"subins": [
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clear_acu,
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sr_read(sr.index("SPL")) | c_qw["TMP_write_en"],
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alu_op(inc.index("DEC"),alu_dev.index("INC")) | sr_write(sr.index("SPL")),
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clear_tmp,
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sr_read(sr.index("SPH")) | c_qw["ACU_write_en"],
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alu_op(alu.index("SBC")) | sr_write(sr.index("SPH")) | c_qw["reset_m_state"] | c_qw["reset_context"]
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]
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}
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z = 4
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for y in range(8):
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if y == r.index("(HL)"): continue
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instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
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"name": f"INC {r[y]}",
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"subins": [
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clear_acu,
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mr_read(y) | c_qw["TMP_write_en"],
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alu_op(inc.index("INC"),alu_dev.index("INC")) | mr_write(y),
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flatch_to_f | c_qw["reset_m_state"] | c_qw["reset_context"]
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]
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}
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z = 4
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y = r.index("(HL)")
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instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
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"name": f"INC (HL)",
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"subins": [
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exec_if_context | sr_read(sr.index("PC")) | mem_read | c_qw["ACU_write_en"] | c_qw["TMP_write_en"] | sr_write(sr.index("Z")),
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exec_if_context | sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
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#sign extend
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exec_if_context | alu_op(alu.index("ADD")),
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exec_if_context | alu_op(alu.index("SBC")) | sr_write(sr.index("W")),
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exec_if_context | mr_read(r.index("L")) | c_qw["ACU_write_en"],
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exec_if_context | sr_read(sr.index("Z")) | c_qw["TMP_write_en"],
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exec_if_context | alu_op(alu.index("ADD")) | sr_write(sr.index("Z")),
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exec_if_context | mr_read(r.index("H")) | c_qw["ACU_write_en"],
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exec_if_context | sr_read(sr.index("W")) | c_qw["TMP_write_en"],
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exec_if_context | alu_op(alu.index("ADC")) | sr_write(sr.index("W")),
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clear_acu,
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mr_read(r.index("(HL)")) | mem_read | c_qw["TMP_write_en"],
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alu_op(inc.index("INC"),alu_dev.index("INC")) | mr_read(y) | mem_write,
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flatch_to_f | c_qw["reset_m_state"] | c_qw["reset_context"]
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]
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}
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z = 5
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for y in range(8):
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if y == r.index("(HL)"): continue
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instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
|
|
"name": f"DEC {r[y]}",
|
|
"subins": [
|
|
clear_acu,
|
|
mr_read(y) | c_qw["TMP_write_en"],
|
|
alu_op(inc.index("DEC"),alu_dev.index("INC")) | mr_write(y),
|
|
flatch_to_f | c_qw["reset_m_state"] | c_qw["reset_context"]
|
|
]
|
|
}
|
|
|
|
z = 5
|
|
y = r.index("(HL)")
|
|
instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
|
|
"name": f"DEC (HL)",
|
|
"subins": [
|
|
exec_if_context | sr_read(sr.index("PC")) | mem_read | c_qw["ACU_write_en"] | c_qw["TMP_write_en"] | sr_write(sr.index("Z")),
|
|
exec_if_context | sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
|
|
|
|
#sign extend
|
|
exec_if_context | alu_op(alu.index("ADD")),
|
|
exec_if_context | alu_op(alu.index("SBC")) | sr_write(sr.index("W")),
|
|
|
|
exec_if_context | mr_read(r.index("L")) | c_qw["ACU_write_en"],
|
|
exec_if_context | sr_read(sr.index("Z")) | c_qw["TMP_write_en"],
|
|
exec_if_context | alu_op(alu.index("ADD")) | sr_write(sr.index("Z")),
|
|
exec_if_context | mr_read(r.index("H")) | c_qw["ACU_write_en"],
|
|
exec_if_context | sr_read(sr.index("W")) | c_qw["TMP_write_en"],
|
|
exec_if_context | alu_op(alu.index("ADC")) | sr_write(sr.index("W")),
|
|
|
|
clear_acu,
|
|
mr_read(r.index("(HL)")) | mem_read | c_qw["TMP_write_en"],
|
|
alu_op(inc.index("DEC"),alu_dev.index("INC")) | mr_read(y) | mem_write,
|
|
flatch_to_f | c_qw["reset_m_state"] | c_qw["reset_context"]
|
|
]
|
|
}
|
|
|
|
z = 6
|
|
for y in range(8):
|
|
if y == r.index("(HL)"): continue
|
|
instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
|
|
"name": f"LD {r[y]}, n",
|
|
"subins": [
|
|
sr_read(sr.index("PC")) | mem_read | mr_write(y) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")) | c_qw["reset_m_state"] | c_qw["reset_context"]
|
|
]
|
|
}
|
|
|
|
z = 6
|
|
y = r.index("(HL)")
|
|
instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
|
|
"name": f"LD (HL), n",
|
|
"subins": [
|
|
exec_if_context | sr_read(sr.index("PC")) | mem_read | c_qw["ACU_write_en"] | c_qw["TMP_write_en"] | sr_write(sr.index("Z")),
|
|
exec_if_context | sr_read(sr.index("PC")) | c_qw["addr_inc_en"] | sr_write(sr.index("PC")),
|
|
|
|
#sign extend
|
|
exec_if_context | alu_op(alu.index("ADD")),
|
|
exec_if_context | alu_op(alu.index("SBC")) | sr_write(sr.index("W")),
|
|
|
|
exec_if_context | mr_read(r.index("L")) | c_qw["ACU_write_en"],
|
|
exec_if_context | sr_read(sr.index("Z")) | c_qw["TMP_write_en"],
|
|
exec_if_context | alu_op(alu.index("ADD")) | sr_write(sr.index("Z")),
|
|
exec_if_context | mr_read(r.index("H")) | c_qw["ACU_write_en"],
|
|
exec_if_context | sr_read(sr.index("W")) | c_qw["TMP_write_en"],
|
|
exec_if_context | alu_op(alu.index("ADC")) | sr_write(sr.index("W")),
|
|
|
|
sr_read(sr.index("PC")) | mem_read | c_qw["TMP_write_en"] | c_qw["addr_inc_en"] | sr_write(sr.index("PC")), # super hacky to preserve WZ for (IX+d)
|
|
|
|
mr_read(r.index("(HL)")) | tmp_to_db | mem_write | c_qw["reset_m_state"] | c_qw["reset_context"] # passthru tmp => DB
|
|
]
|
|
}
|
|
|
|
z = 7
|
|
y = 0
|
|
instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
|
|
"name": "RLCA",
|
|
"subins": [
|
|
f_to_flatch,
|
|
mr_read(r.index("A")) | c_qw["TMP_write_en"],
|
|
alu_op(rot.index("RLC"),alu_dev.index("SLU")) | mr_write(r.index("A")),
|
|
|
|
c_qw["Flatch_read_en"] | c_qw["ACU_write_en"],
|
|
clear_tmp,
|
|
alu_op(flags.index("C") | bit["SET"],alu_dev.index("BMU")) | c_qw["TMP_write_en"],
|
|
alu_op(alu.index("AND")) | sr_write(sr.index("Z")),
|
|
|
|
internal_byte_to_db(internal_byte.index("FF")) | c_qw["TMP_write_en"],
|
|
alu_op(flags.index("C") | bit["RESET"],alu_dev.index("BMU")) | c_qw["TMP_write_en"],
|
|
alu_op(flags.index("H") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
|
|
alu_op(flags.index("N") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"], #W = 0b11101100
|
|
c_qw["F_read_en"] | c_qw["ACU_write_en"],
|
|
alu_op(alu.index("AND")) | c_qw["ACU_write_en"],
|
|
|
|
sr_write(sr.index("Z")) | c_qw["TMP_write_en"],
|
|
alu_op(alu.index("OR")) | c_qw["F_write_en"]| c_qw["reset_m_state"] | c_qw["reset_context"]
|
|
]
|
|
}
|
|
|
|
z = 7
|
|
y = 1
|
|
instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
|
|
"name": "RRCA",
|
|
"subins": [
|
|
f_to_flatch,
|
|
mr_read(r.index("A")) | c_qw["TMP_write_en"],
|
|
alu_op(rot.index("RRC"),alu_dev.index("SLU")) | mr_write(r.index("A")),
|
|
|
|
c_qw["Flatch_read_en"] | c_qw["ACU_write_en"],
|
|
clear_tmp,
|
|
alu_op(flags.index("C") | bit["SET"],alu_dev.index("BMU")) | c_qw["TMP_write_en"],
|
|
alu_op(alu.index("AND")) | sr_write(sr.index("Z")), # Z = 0b0000000C
|
|
|
|
internal_byte_to_db(internal_byte.index("FF")) | c_qw["TMP_write_en"],
|
|
alu_op(flags.index("C") | bit["RESET"],alu_dev.index("BMU")) | c_qw["TMP_write_en"],
|
|
alu_op(flags.index("H") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
|
|
alu_op(flags.index("N") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"], #W = 0b11101100
|
|
c_qw["F_read_en"] | c_qw["ACU_write_en"],
|
|
alu_op(alu.index("AND")) | c_qw["ACU_write_en"],
|
|
|
|
sr_write(sr.index("Z")) | c_qw["TMP_write_en"],
|
|
alu_op(alu.index("OR")) | c_qw["F_write_en"]| c_qw["reset_m_state"] | c_qw["reset_context"]
|
|
]
|
|
}
|
|
|
|
z = 7
|
|
y = 2
|
|
instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
|
|
"name": "RLA",
|
|
"subins": [
|
|
mr_read(r.index("A")) | c_qw["TMP_write_en"],
|
|
alu_op(rot.index("RL"),alu_dev.index("SLU"))| mr_write(r.index("A")),
|
|
|
|
c_qw["Flatch_read_en"] | c_qw["ACU_write_en"],
|
|
clear_tmp,
|
|
alu_op(flags.index("C") | bit["SET"],alu_dev.index("BMU")) | c_qw["TMP_write_en"],
|
|
alu_op(alu.index("AND")) | sr_write(sr.index("Z")), # Z = 0b0000000C
|
|
|
|
internal_byte_to_db(internal_byte.index("FF")) | c_qw["TMP_write_en"],
|
|
alu_op(flags.index("C") | bit["RESET"],alu_dev.index("BMU")) | c_qw["TMP_write_en"],
|
|
alu_op(flags.index("H") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
|
|
alu_op(flags.index("N") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"], #W = 0b11101100
|
|
c_qw["F_read_en"] | c_qw["ACU_write_en"],
|
|
alu_op(alu.index("AND")) | c_qw["ACU_write_en"],
|
|
|
|
sr_write(sr.index("Z")) | c_qw["TMP_write_en"],
|
|
alu_op(alu.index("OR")) | c_qw["F_write_en"]| c_qw["reset_m_state"] | c_qw["reset_context"]
|
|
]
|
|
}
|
|
|
|
z = 7
|
|
y = 3
|
|
instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
|
|
"name": "RRA",
|
|
"subins": [
|
|
mr_read(r.index("A")) | c_qw["TMP_write_en"],
|
|
alu_op(rot.index("RR"),alu_dev.index("SLU"))| mr_write(r.index("A")),
|
|
|
|
c_qw["Flatch_read_en"] | c_qw["ACU_write_en"],
|
|
clear_tmp,
|
|
alu_op(flags.index("C") | bit["SET"],alu_dev.index("BMU")) | c_qw["TMP_write_en"],
|
|
alu_op(alu.index("AND")) | sr_write(sr.index("Z")), # Z = 0b0000000C
|
|
|
|
internal_byte_to_db(internal_byte.index("FF")) | c_qw["TMP_write_en"],
|
|
alu_op(flags.index("C") | bit["RESET"],alu_dev.index("BMU")) | c_qw["TMP_write_en"],
|
|
alu_op(flags.index("H") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
|
|
alu_op(flags.index("N") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"], #W = 0b11101100
|
|
c_qw["F_read_en"] | c_qw["ACU_write_en"],
|
|
alu_op(alu.index("AND")) | c_qw["ACU_write_en"],
|
|
|
|
sr_write(sr.index("Z")) | c_qw["TMP_write_en"],
|
|
alu_op(alu.index("OR")) | c_qw["F_write_en"] | c_qw["reset_m_state"] | c_qw["reset_context"]
|
|
]
|
|
}
|
|
|
|
z = 7
|
|
y = 4
|
|
instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
|
|
"name": "DAA",
|
|
"subins": [
|
|
f_to_flatch,
|
|
a_to_acu,
|
|
alu_op(0,alu_dev.index("DAA")) | mr_write(r.index("A")),
|
|
flatch_to_f | c_qw["reset_m_state"] | c_qw["reset_context"]
|
|
]
|
|
}
|
|
|
|
z = 7
|
|
y = 5
|
|
instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
|
|
"name": "CPL",
|
|
"subins": [
|
|
a_to_acu,
|
|
alu_op(alu.index("NOT"),save_flags=False) | mr_write(r.index("A")),
|
|
f_to_tmp,
|
|
alu_op(flags.index("H") | bit["SET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
|
|
alu_op(flags.index("N") | bit["SET"],alu_dev.index("BMU"),False) | c_qw["F_write_en"] | c_qw["reset_m_state"] | c_qw["reset_context"]
|
|
]
|
|
}
|
|
|
|
z = 7
|
|
y = 6
|
|
instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
|
|
"name": "SCF",
|
|
"subins": [
|
|
f_to_tmp,
|
|
alu_op(flags.index("C") | bit["SET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
|
|
alu_op(flags.index("H") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
|
|
alu_op(flags.index("N") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["F_write_en"] | c_qw["reset_m_state"] | c_qw["reset_context"]
|
|
]
|
|
}
|
|
|
|
z = 7
|
|
y = 7
|
|
instructions[int(f"0b00{y:03b}{z:03b}", 2)] = {
|
|
"name": "CCF",
|
|
"subins": [
|
|
f_to_acu,
|
|
clear_tmp,
|
|
alu_op(flags.index("C") | bit["SET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
|
|
alu_op(flags.index("H") | bit["SET"],alu_dev.index("BMU"),False) | c_qw["TMP_write_en"],
|
|
alu_op(alu.index("XOR"),save_flags=False) | c_qw["TMP_write_en"],
|
|
alu_op(flags.index("N") | bit["RESET"],alu_dev.index("BMU"),False) | c_qw["F_write_en"] | c_qw["reset_m_state"] | c_qw["reset_context"]
|
|
]
|
|
} |